282 lines
8.3 KiB
C
282 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Eliot Lee <eliot.lee@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/types.h>
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#include "t7xx_cldma.h"
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#define ADDR_SIZE 8
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void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
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{
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u32 val;
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val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
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val |= IP_BUSY_WAKEUP;
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iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
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}
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/**
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* t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
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* @hw_info: Pointer to struct t7xx_cldma_hw.
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*
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* Restore HW after resume. Writes uplink configuration for CLDMA HW.
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*/
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void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
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{
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u32 ul_cfg;
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ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
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if (hw_info->hw_mode == MODE_BIT_64)
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ul_cfg |= UL_CFG_BIT_MODE_64;
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else if (hw_info->hw_mode == MODE_BIT_40)
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ul_cfg |= UL_CFG_BIT_MODE_40;
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else if (hw_info->hw_mode == MODE_BIT_36)
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ul_cfg |= UL_CFG_BIT_MODE_36;
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iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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/* Disable TX and RX invalid address check */
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iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
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iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
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}
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void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
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hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
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{
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/* Enable the TX & RX interrupts */
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iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
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iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
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/* Enable the empty queue interrupt */
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iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
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iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
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}
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void t7xx_cldma_hw_reset(void __iomem *ao_base)
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{
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u32 val;
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val = ioread32(ao_base + REG_INFRA_RST2_SET);
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val |= RST2_PMIC_SW_RST_SET;
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iowrite32(val, ao_base + REG_INFRA_RST2_SET);
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val = ioread32(ao_base + REG_INFRA_RST4_SET);
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val |= RST4_CLDMA1_SW_RST_SET;
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iowrite32(val, ao_base + REG_INFRA_RST4_SET);
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udelay(1);
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val = ioread32(ao_base + REG_INFRA_RST4_CLR);
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val |= RST4_CLDMA1_SW_RST_CLR;
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iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
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val = ioread32(ao_base + REG_INFRA_RST2_CLR);
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val |= RST2_PMIC_SW_RST_CLR;
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iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
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}
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bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno)
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{
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u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE;
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return ioread64(hw_info->ap_pdn_base + offset);
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}
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void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address,
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enum mtk_txrx tx_rx)
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{
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u32 offset = qno * ADDR_SIZE;
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 :
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hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;
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iowrite64(address, reg + offset);
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}
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void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *base = hw_info->ap_pdn_base;
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if (tx_rx == MTK_RX)
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iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
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else
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iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
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}
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unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 mask, val;
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mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS :
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hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;
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val = ioread32(reg);
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return val & mask;
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}
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void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
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{
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unsigned int ch_id;
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ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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ch_id &= bitmask;
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/* Clear the ch IDs in the TX interrupt status register */
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iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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}
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void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
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{
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unsigned int ch_id;
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ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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ch_id &= bitmask;
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/* Clear the ch IDs in the RX interrupt status register */
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iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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}
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unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;
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val = ioread32(reg);
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return val & bitmask;
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}
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void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val << EQ_STA_BIT_OFFSET, reg);
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}
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void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val << EQ_STA_BIT_OFFSET, reg);
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}
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/**
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* t7xx_cldma_hw_init() - Initialize CLDMA HW.
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* @hw_info: Pointer to struct t7xx_cldma_hw.
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*
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* Write uplink and downlink configuration to CLDMA HW.
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*/
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void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info)
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{
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u32 ul_cfg, dl_cfg;
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ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
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/* Configure the DRAM address mode */
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ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
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dl_cfg &= ~DL_CFG_BIT_MODE_MASK;
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if (hw_info->hw_mode == MODE_BIT_64) {
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ul_cfg |= UL_CFG_BIT_MODE_64;
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dl_cfg |= DL_CFG_BIT_MODE_64;
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} else if (hw_info->hw_mode == MODE_BIT_40) {
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ul_cfg |= UL_CFG_BIT_MODE_40;
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dl_cfg |= DL_CFG_BIT_MODE_40;
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} else if (hw_info->hw_mode == MODE_BIT_36) {
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ul_cfg |= UL_CFG_BIT_MODE_36;
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dl_cfg |= DL_CFG_BIT_MODE_36;
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}
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iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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dl_cfg |= DL_CFG_UP_HW_LAST;
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iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
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iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
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iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
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iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
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iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
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}
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void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :
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hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;
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iowrite32(CLDMA_ALL_Q, reg);
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}
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void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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iowrite32(TXRX_STATUS_BITMASK, reg);
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iowrite32(EMPTY_STATUS_BITMASK, reg);
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}
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