381 lines
9.5 KiB
C
381 lines
9.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
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* such as Graviton and Alpine)
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*
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* Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Author: Jonathan Chocron <jonnyc@amazon.com>
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*/
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/pci-acpi.h>
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#include "../../pci.h"
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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struct al_pcie_acpi {
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void __iomem *dbi_base;
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};
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static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct al_pcie_acpi *pcie = cfg->priv;
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void __iomem *dbi_base = pcie->dbi_base;
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if (bus->number == cfg->busr.start) {
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/*
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* The DW PCIe core doesn't filter out transactions to other
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* devices/functions on the root bus num, so we do this here.
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*/
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if (PCI_SLOT(devfn) > 0)
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return NULL;
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else
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return dbi_base + where;
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}
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return pci_ecam_map_bus(bus, devfn, where);
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}
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static int al_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct al_pcie_acpi *al_pcie;
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struct resource *res;
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int ret;
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al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
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if (!al_pcie)
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return -ENOMEM;
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res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);
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if (ret) {
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dev_err(dev, "can't get rc dbi base address for SEG %d\n",
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root->segment);
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return ret;
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}
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dev_dbg(dev, "Root port dbi res: %pR\n", res);
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al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(al_pcie->dbi_base))
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return PTR_ERR(al_pcie->dbi_base);
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cfg->priv = al_pcie;
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return 0;
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}
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const struct pci_ecam_ops al_pcie_ops = {
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.init = al_pcie_init,
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.pci_ops = {
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.map_bus = al_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
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#ifdef CONFIG_PCIE_AL
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#include <linux/of_pci.h>
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#include "pcie-designware.h"
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#define AL_PCIE_REV_ID_2 2
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#define AL_PCIE_REV_ID_3 3
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#define AL_PCIE_REV_ID_4 4
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#define AXI_BASE_OFFSET 0x0
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#define DEVICE_ID_OFFSET 0x16c
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#define DEVICE_REV_ID 0x0
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#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
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#define DEVICE_REV_ID_DEV_ID_X4 0
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#define DEVICE_REV_ID_DEV_ID_X8 2
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#define DEVICE_REV_ID_DEV_ID_X16 4
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#define OB_CTRL_REV1_2_OFFSET 0x0040
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#define OB_CTRL_REV3_5_OFFSET 0x0030
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#define CFG_TARGET_BUS 0x0
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#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
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#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
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#define CFG_CONTROL 0x4
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#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
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#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
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struct al_pcie_reg_offsets {
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unsigned int ob_ctrl;
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};
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struct al_pcie_target_bus_cfg {
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u8 reg_val;
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u8 reg_mask;
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u8 ecam_mask;
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};
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struct al_pcie {
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struct dw_pcie *pci;
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void __iomem *controller_base; /* base of PCIe unit (not DW core) */
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struct device *dev;
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resource_size_t ecam_size;
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unsigned int controller_rev_id;
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struct al_pcie_reg_offsets reg_offsets;
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struct al_pcie_target_bus_cfg target_bus_cfg;
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};
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#define to_al_pcie(x) dev_get_drvdata((x)->dev)
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static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)
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{
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return readl_relaxed(pcie->controller_base + offset);
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}
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static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,
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u32 val)
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{
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writel_relaxed(val, pcie->controller_base + offset);
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}
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static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
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{
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u32 dev_rev_id_val;
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u32 dev_id_val;
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dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +
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DEVICE_ID_OFFSET +
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DEVICE_REV_ID);
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dev_id_val = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK, dev_rev_id_val);
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switch (dev_id_val) {
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case DEVICE_REV_ID_DEV_ID_X4:
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*rev_id = AL_PCIE_REV_ID_2;
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break;
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case DEVICE_REV_ID_DEV_ID_X8:
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*rev_id = AL_PCIE_REV_ID_3;
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break;
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case DEVICE_REV_ID_DEV_ID_X16:
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*rev_id = AL_PCIE_REV_ID_4;
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break;
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default:
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dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",
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dev_id_val);
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return -EINVAL;
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}
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dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);
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return 0;
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}
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static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
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{
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switch (pcie->controller_rev_id) {
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case AL_PCIE_REV_ID_2:
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pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
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break;
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case AL_PCIE_REV_ID_3:
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case AL_PCIE_REV_ID_4:
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pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
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break;
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default:
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dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
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pcie->controller_rev_id);
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return -EINVAL;
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}
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return 0;
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}
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static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
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u8 target_bus,
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u8 mask_target_bus)
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{
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u32 reg;
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reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
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FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
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al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +
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pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,
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reg);
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}
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static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct dw_pcie_rp *pp = bus->sysdata;
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struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
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unsigned int busnr = bus->number;
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struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
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unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
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unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
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if (busnr_reg != target_bus_cfg->reg_val) {
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dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
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target_bus_cfg->reg_val, busnr_reg);
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target_bus_cfg->reg_val = busnr_reg;
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al_pcie_target_bus_set(pcie,
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target_bus_cfg->reg_val,
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target_bus_cfg->reg_mask);
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}
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return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where);
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}
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static struct pci_ops al_child_pci_ops = {
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.map_bus = al_pcie_conf_addr_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static void al_pcie_config_prepare(struct al_pcie *pcie)
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{
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struct al_pcie_target_bus_cfg *target_bus_cfg;
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struct dw_pcie_rp *pp = &pcie->pci->pp;
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unsigned int ecam_bus_mask;
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u32 cfg_control_offset;
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u8 subordinate_bus;
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u8 secondary_bus;
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u32 cfg_control;
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u32 reg;
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struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
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target_bus_cfg = &pcie->target_bus_cfg;
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ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1;
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if (ecam_bus_mask > 255) {
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dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
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ecam_bus_mask = 255;
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}
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/* This portion is taken from the transaction address */
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target_bus_cfg->ecam_mask = ecam_bus_mask;
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/* This portion is taken from the cfg_target_bus reg */
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target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
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target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;
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al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
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target_bus_cfg->reg_mask);
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secondary_bus = bus->start + 1;
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subordinate_bus = bus->end;
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/* Set the valid values of secondary and subordinate buses */
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cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
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CFG_CONTROL;
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cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
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reg = cfg_control &
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~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
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reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
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FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
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al_pcie_controller_writel(pcie, cfg_control_offset, reg);
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}
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static int al_pcie_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct al_pcie *pcie = to_al_pcie(pci);
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int rc;
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pp->bridge->child_ops = &al_child_pci_ops;
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rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
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if (rc)
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return rc;
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rc = al_pcie_reg_offsets_set(pcie);
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if (rc)
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return rc;
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al_pcie_config_prepare(pcie);
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return 0;
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}
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static const struct dw_pcie_host_ops al_pcie_host_ops = {
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.host_init = al_pcie_host_init,
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};
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static int al_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *controller_res;
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struct resource *ecam_res;
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struct al_pcie *al_pcie;
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struct dw_pcie *pci;
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al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
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if (!al_pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->pp.ops = &al_pcie_host_ops;
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al_pcie->pci = pci;
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al_pcie->dev = dev;
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ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (!ecam_res) {
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dev_err(dev, "couldn't find 'config' reg in DT\n");
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return -ENOENT;
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}
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al_pcie->ecam_size = resource_size(ecam_res);
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controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"controller");
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al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
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if (IS_ERR(al_pcie->controller_base)) {
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dev_err(dev, "couldn't remap controller base %pR\n",
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controller_res);
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return PTR_ERR(al_pcie->controller_base);
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}
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dev_dbg(dev, "From DT: controller_base: %pR\n", controller_res);
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, al_pcie);
|
||
|
|
|
||
|
|
return dw_pcie_host_init(&pci->pp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id al_pcie_of_match[] = {
|
||
|
|
{ .compatible = "amazon,al-alpine-v2-pcie",
|
||
|
|
},
|
||
|
|
{ .compatible = "amazon,al-alpine-v3-pcie",
|
||
|
|
},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver al_pcie_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "al-pcie",
|
||
|
|
.of_match_table = al_pcie_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
.probe = al_pcie_probe,
|
||
|
|
};
|
||
|
|
builtin_platform_driver(al_pcie_driver);
|
||
|
|
|
||
|
|
#endif /* CONFIG_PCIE_AL*/
|