424 lines
11 KiB
C
424 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip AXI PCIe host controller driver
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*
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* Copyright (c) 2016 Rockchip, Inc.
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*
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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* Wenrui Li <wenrui.li@rock-chips.com>
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*
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* Bits taken from Synopsys DesignWare Host controller driver and
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* ARM PCI Host generic driver.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "../pci.h"
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#include "pcie-rockchip.h"
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int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *node = dev->of_node;
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struct resource *regs;
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int err;
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if (rockchip->is_rc) {
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regs = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"axi-base");
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rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(rockchip->reg_base))
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return PTR_ERR(rockchip->reg_base);
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} else {
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rockchip->mem_res =
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platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"mem-base");
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if (!rockchip->mem_res)
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return -EINVAL;
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}
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rockchip->apb_base =
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devm_platform_ioremap_resource_byname(pdev, "apb-base");
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if (IS_ERR(rockchip->apb_base))
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return PTR_ERR(rockchip->apb_base);
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err = rockchip_pcie_get_phys(rockchip);
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if (err)
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return err;
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rockchip->lanes = 1;
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err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
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if (!err && (rockchip->lanes == 0 ||
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rockchip->lanes == 3 ||
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rockchip->lanes > 4)) {
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dev_warn(dev, "invalid num-lanes, default to use one lane\n");
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rockchip->lanes = 1;
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}
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rockchip->link_gen = of_pci_get_max_link_speed(node);
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if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
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rockchip->link_gen = 2;
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rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
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if (IS_ERR(rockchip->core_rst)) {
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if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing core reset property in node\n");
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return PTR_ERR(rockchip->core_rst);
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}
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rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
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if (IS_ERR(rockchip->mgmt_rst)) {
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if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt reset property in node\n");
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return PTR_ERR(rockchip->mgmt_rst);
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}
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rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
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"mgmt-sticky");
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if (IS_ERR(rockchip->mgmt_sticky_rst)) {
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if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt-sticky reset property in node\n");
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return PTR_ERR(rockchip->mgmt_sticky_rst);
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}
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rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
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if (IS_ERR(rockchip->pipe_rst)) {
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if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pipe reset property in node\n");
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return PTR_ERR(rockchip->pipe_rst);
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}
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rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
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if (IS_ERR(rockchip->pm_rst)) {
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if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pm reset property in node\n");
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return PTR_ERR(rockchip->pm_rst);
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}
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rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
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if (IS_ERR(rockchip->pclk_rst)) {
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if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pclk reset property in node\n");
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return PTR_ERR(rockchip->pclk_rst);
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}
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rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
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if (IS_ERR(rockchip->aclk_rst)) {
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if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing aclk reset property in node\n");
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return PTR_ERR(rockchip->aclk_rst);
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}
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if (rockchip->is_rc) {
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rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
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GPIOD_OUT_HIGH);
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if (IS_ERR(rockchip->ep_gpio))
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return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
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"failed to get ep GPIO\n");
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}
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rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
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if (IS_ERR(rockchip->aclk_pcie)) {
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dev_err(dev, "aclk clock not found\n");
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return PTR_ERR(rockchip->aclk_pcie);
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}
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rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
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if (IS_ERR(rockchip->aclk_perf_pcie)) {
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dev_err(dev, "aclk_perf clock not found\n");
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return PTR_ERR(rockchip->aclk_perf_pcie);
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}
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rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
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if (IS_ERR(rockchip->hclk_pcie)) {
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dev_err(dev, "hclk clock not found\n");
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return PTR_ERR(rockchip->hclk_pcie);
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}
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rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
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if (IS_ERR(rockchip->clk_pcie_pm)) {
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dev_err(dev, "pm clock not found\n");
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return PTR_ERR(rockchip->clk_pcie_pm);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
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int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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int err, i;
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u32 regs;
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err = reset_control_assert(rockchip->aclk_rst);
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if (err) {
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dev_err(dev, "assert aclk_rst err %d\n", err);
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return err;
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}
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err = reset_control_assert(rockchip->pclk_rst);
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if (err) {
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dev_err(dev, "assert pclk_rst err %d\n", err);
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return err;
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}
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err = reset_control_assert(rockchip->pm_rst);
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if (err) {
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dev_err(dev, "assert pm_rst err %d\n", err);
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return err;
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}
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for (i = 0; i < MAX_LANE_NUM; i++) {
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err = phy_init(rockchip->phys[i]);
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if (err) {
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dev_err(dev, "init phy%d err %d\n", i, err);
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goto err_exit_phy;
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}
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}
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err = reset_control_assert(rockchip->core_rst);
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if (err) {
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dev_err(dev, "assert core_rst err %d\n", err);
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goto err_exit_phy;
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}
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err = reset_control_assert(rockchip->mgmt_rst);
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if (err) {
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dev_err(dev, "assert mgmt_rst err %d\n", err);
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goto err_exit_phy;
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}
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err = reset_control_assert(rockchip->mgmt_sticky_rst);
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if (err) {
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dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
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goto err_exit_phy;
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}
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err = reset_control_assert(rockchip->pipe_rst);
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if (err) {
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dev_err(dev, "assert pipe_rst err %d\n", err);
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goto err_exit_phy;
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}
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udelay(10);
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err = reset_control_deassert(rockchip->pm_rst);
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if (err) {
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dev_err(dev, "deassert pm_rst err %d\n", err);
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goto err_exit_phy;
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}
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err = reset_control_deassert(rockchip->aclk_rst);
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if (err) {
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dev_err(dev, "deassert aclk_rst err %d\n", err);
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goto err_exit_phy;
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}
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err = reset_control_deassert(rockchip->pclk_rst);
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if (err) {
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dev_err(dev, "deassert pclk_rst err %d\n", err);
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goto err_exit_phy;
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}
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if (rockchip->link_gen == 2)
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rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
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PCIE_CLIENT_CONFIG);
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else
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rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
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PCIE_CLIENT_CONFIG);
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regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |
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PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
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if (rockchip->is_rc)
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regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
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else
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regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
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rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
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for (i = 0; i < MAX_LANE_NUM; i++) {
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err = phy_power_on(rockchip->phys[i]);
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if (err) {
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dev_err(dev, "power on phy%d err %d\n", i, err);
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goto err_power_off_phy;
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}
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}
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/*
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* Please don't reorder the deassert sequence of the following
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* four reset pins.
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*/
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err = reset_control_deassert(rockchip->mgmt_sticky_rst);
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if (err) {
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dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
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goto err_power_off_phy;
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}
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err = reset_control_deassert(rockchip->core_rst);
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if (err) {
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dev_err(dev, "deassert core_rst err %d\n", err);
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goto err_power_off_phy;
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}
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err = reset_control_deassert(rockchip->mgmt_rst);
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if (err) {
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dev_err(dev, "deassert mgmt_rst err %d\n", err);
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goto err_power_off_phy;
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}
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err = reset_control_deassert(rockchip->pipe_rst);
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if (err) {
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dev_err(dev, "deassert pipe_rst err %d\n", err);
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goto err_power_off_phy;
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}
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return 0;
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err_power_off_phy:
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while (i--)
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phy_power_off(rockchip->phys[i]);
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i = MAX_LANE_NUM;
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err_exit_phy:
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while (i--)
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phy_exit(rockchip->phys[i]);
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return err;
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_init_port);
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int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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struct phy *phy;
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char *name;
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u32 i;
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phy = devm_phy_get(dev, "pcie-phy");
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if (!IS_ERR(phy)) {
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rockchip->legacy_phy = true;
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rockchip->phys[0] = phy;
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dev_warn(dev, "legacy phy model is deprecated!\n");
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return 0;
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}
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if (PTR_ERR(phy) == -EPROBE_DEFER)
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return PTR_ERR(phy);
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dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
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for (i = 0; i < MAX_LANE_NUM; i++) {
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name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
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if (!name)
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return -ENOMEM;
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phy = devm_of_phy_get(dev, dev->of_node, name);
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kfree(name);
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if (IS_ERR(phy)) {
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if (PTR_ERR(phy) != -EPROBE_DEFER)
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dev_err(dev, "missing phy for lane %d: %ld\n",
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i, PTR_ERR(phy));
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return PTR_ERR(phy);
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}
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rockchip->phys[i] = phy;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys);
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void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
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{
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int i;
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for (i = 0; i < MAX_LANE_NUM; i++) {
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/* inactive lanes are already powered off */
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if (rockchip->lanes_map & BIT(i))
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phy_power_off(rockchip->phys[i]);
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phy_exit(rockchip->phys[i]);
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}
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys);
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int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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||
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|
int err;
|
||
|
|
|
||
|
|
err = clk_prepare_enable(rockchip->aclk_pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "unable to enable aclk_pcie clock\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
|
||
|
|
goto err_aclk_perf_pcie;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = clk_prepare_enable(rockchip->hclk_pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "unable to enable hclk_pcie clock\n");
|
||
|
|
goto err_hclk_pcie;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = clk_prepare_enable(rockchip->clk_pcie_pm);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "unable to enable clk_pcie_pm clock\n");
|
||
|
|
goto err_clk_pcie_pm;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_clk_pcie_pm:
|
||
|
|
clk_disable_unprepare(rockchip->hclk_pcie);
|
||
|
|
err_hclk_pcie:
|
||
|
|
clk_disable_unprepare(rockchip->aclk_perf_pcie);
|
||
|
|
err_aclk_perf_pcie:
|
||
|
|
clk_disable_unprepare(rockchip->aclk_pcie);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
|
||
|
|
|
||
|
|
void rockchip_pcie_disable_clocks(void *data)
|
||
|
|
{
|
||
|
|
struct rockchip_pcie *rockchip = data;
|
||
|
|
|
||
|
|
clk_disable_unprepare(rockchip->clk_pcie_pm);
|
||
|
|
clk_disable_unprepare(rockchip->hclk_pcie);
|
||
|
|
clk_disable_unprepare(rockchip->aclk_perf_pcie);
|
||
|
|
clk_disable_unprepare(rockchip->aclk_pcie);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
|
||
|
|
|
||
|
|
void rockchip_pcie_cfg_configuration_accesses(
|
||
|
|
struct rockchip_pcie *rockchip, u32 type)
|
||
|
|
{
|
||
|
|
u32 ob_desc_0;
|
||
|
|
|
||
|
|
/* Configuration Accesses for region 0 */
|
||
|
|
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
|
||
|
|
|
||
|
|
rockchip_pcie_write(rockchip,
|
||
|
|
(RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
|
||
|
|
PCIE_CORE_OB_REGION_ADDR0);
|
||
|
|
rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
|
||
|
|
PCIE_CORE_OB_REGION_ADDR1);
|
||
|
|
ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
|
||
|
|
ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
|
||
|
|
ob_desc_0 |= (type | (0x1 << 23));
|
||
|
|
rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
|
||
|
|
rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);
|