333 lines
8.7 KiB
C
333 lines
8.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2019, Linaro Ltd.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/phy/phy.h>
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#define PCIE20_PARF_PHY_STTS 0x3c
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#define PCIE2_PHY_RESET_CTRL 0x44
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#define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
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#define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
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#define PCIE20_PARF_PCS_SWING_CTRL1 0x88
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#define PCIE20_PARF_PCS_SWING_CTRL2 0x8c
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#define PCIE20_PARF_PCS_DEEMPH1 0x74
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#define PCIE20_PARF_PCS_DEEMPH2 0x78
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#define PCIE20_PARF_PCS_DEEMPH3 0x7c
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#define PCIE20_PARF_CONFIGBITS 0x84
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#define PCIE20_PARF_PHY_CTRL3 0x94
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#define PCIE20_PARF_PCS_CTRL 0x80
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#define TX_AMP_VAL 120
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#define PHY_RX0_EQ_GEN1_VAL 0
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#define PHY_RX0_EQ_GEN2_VAL 4
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#define TX_DEEMPH_GEN1_VAL 24
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#define TX_DEEMPH_GEN2_3_5DB_VAL 26
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#define TX_DEEMPH_GEN2_6DB_VAL 36
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#define PHY_TX0_TERM_OFFST_VAL 0
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struct qcom_phy {
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struct device *dev;
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void __iomem *base;
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struct regulator_bulk_data vregs[2];
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struct reset_control *phy_reset;
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struct reset_control *pipe_reset;
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struct clk *pipe_clk;
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};
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static int qcom_pcie2_phy_init(struct phy *phy)
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{
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struct qcom_phy *qphy = phy_get_drvdata(phy);
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int ret;
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ret = reset_control_deassert(qphy->phy_reset);
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if (ret) {
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dev_err(qphy->dev, "cannot deassert pipe reset\n");
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return ret;
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}
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ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
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if (ret)
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reset_control_assert(qphy->phy_reset);
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return ret;
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}
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static int qcom_pcie2_phy_power_on(struct phy *phy)
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{
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struct qcom_phy *qphy = phy_get_drvdata(phy);
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int ret;
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u32 val;
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/* Program REF_CLK source */
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val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
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val &= ~BIT(1);
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writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
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usleep_range(1000, 2000);
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/* Don't use PAD for refclock */
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val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
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val &= ~BIT(0);
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writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
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/* Program SSP ENABLE */
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val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
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val |= BIT(0);
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writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
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usleep_range(1000, 2000);
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/* Assert Phy SW Reset */
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val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
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val |= BIT(0);
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writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
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/* Program Tx Amplitude */
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val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
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val &= ~0x7f;
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val |= TX_AMP_VAL;
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writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
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val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
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val &= ~0x7f;
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val |= TX_AMP_VAL;
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writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
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/* Program De-Emphasis */
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val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
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val &= ~0x3f;
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val |= TX_DEEMPH_GEN2_6DB_VAL;
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writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
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val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
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val &= ~0x3f;
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val |= TX_DEEMPH_GEN2_3_5DB_VAL;
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writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
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val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
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val &= ~0x3f;
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val |= TX_DEEMPH_GEN1_VAL;
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writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
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/* Program Rx_Eq */
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val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
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val &= ~0x7;
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val |= PHY_RX0_EQ_GEN2_VAL;
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writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
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/* Program Tx0_term_offset */
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val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
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val &= ~0x1f;
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val |= PHY_TX0_TERM_OFFST_VAL;
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writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
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/* disable Tx2Rx Loopback */
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val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
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val &= ~BIT(1);
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writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
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/* De-assert Phy SW Reset */
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val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
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val &= ~BIT(0);
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writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
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usleep_range(1000, 2000);
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ret = reset_control_deassert(qphy->pipe_reset);
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if (ret) {
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dev_err(qphy->dev, "cannot deassert pipe reset\n");
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goto out;
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}
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clk_set_rate(qphy->pipe_clk, 250000000);
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ret = clk_prepare_enable(qphy->pipe_clk);
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if (ret) {
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dev_err(qphy->dev, "failed to enable pipe clock\n");
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goto out;
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}
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ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
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!(val & BIT(0)), 1000, 10);
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if (ret)
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dev_err(qphy->dev, "phy initialization failed\n");
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out:
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return ret;
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}
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static int qcom_pcie2_phy_power_off(struct phy *phy)
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{
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struct qcom_phy *qphy = phy_get_drvdata(phy);
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u32 val;
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val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
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val |= BIT(0);
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writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
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clk_disable_unprepare(qphy->pipe_clk);
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reset_control_assert(qphy->pipe_reset);
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return 0;
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}
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static int qcom_pcie2_phy_exit(struct phy *phy)
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{
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struct qcom_phy *qphy = phy_get_drvdata(phy);
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regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
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reset_control_assert(qphy->phy_reset);
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return 0;
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}
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static const struct phy_ops qcom_pcie2_ops = {
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.init = qcom_pcie2_phy_init,
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.power_on = qcom_pcie2_phy_power_on,
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.power_off = qcom_pcie2_phy_power_off,
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.exit = qcom_pcie2_phy_exit,
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.owner = THIS_MODULE,
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};
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/*
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* Register a fixed rate pipe clock.
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*
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* The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
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* controls it. The <s>_pipe_clk coming out of the GCC is requested
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* by the PHY driver for its operations.
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* We register the <s>_pipe_clksrc here. The gcc driver takes care
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* of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
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* Below picture shows this relationship.
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*
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* +---------------+
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* | PHY block |<<---------------------------------------+
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* | | |
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* | +-------+ | +-----+ |
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* I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
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* clk | +-------+ | +-----+
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* +---------------+
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*/
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static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
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{
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struct device_node *np = qphy->dev->of_node;
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struct clk_fixed_rate *fixed;
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struct clk_init_data init = { };
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int ret;
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ret = of_property_read_string(np, "clock-output-names", &init.name);
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if (ret) {
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dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
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return ret;
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}
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fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
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if (!fixed)
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return -ENOMEM;
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init.ops = &clk_fixed_rate_ops;
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/* controllers using QMP phys use 250MHz pipe clock interface */
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fixed->fixed_rate = 250000000;
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fixed->hw.init = &init;
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ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
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if (ret < 0)
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return ret;
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return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
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}
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static int qcom_pcie2_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct qcom_phy *qphy;
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struct device *dev = &pdev->dev;
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struct phy *phy;
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int ret;
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qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
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if (!qphy)
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return -ENOMEM;
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qphy->dev = dev;
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qphy->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(qphy->base))
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return PTR_ERR(qphy->base);
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ret = phy_pipe_clksrc_register(qphy);
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if (ret) {
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dev_err(dev, "failed to register pipe_clk\n");
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return ret;
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}
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qphy->vregs[0].supply = "vdda-vp";
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qphy->vregs[1].supply = "vdda-vph";
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ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
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if (ret < 0)
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return ret;
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qphy->pipe_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(qphy->pipe_clk)) {
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dev_err(dev, "failed to acquire pipe clock\n");
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return PTR_ERR(qphy->pipe_clk);
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}
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qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
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if (IS_ERR(qphy->phy_reset)) {
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dev_err(dev, "failed to acquire phy reset\n");
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return PTR_ERR(qphy->phy_reset);
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}
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qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
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if (IS_ERR(qphy->pipe_reset)) {
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dev_err(dev, "failed to acquire pipe reset\n");
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return PTR_ERR(qphy->pipe_reset);
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}
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phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create phy\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, qphy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider))
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dev_err(dev, "failed to register phy provider\n");
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id qcom_pcie2_phy_match_table[] = {
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{ .compatible = "qcom,pcie2-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table);
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static struct platform_driver qcom_pcie2_phy_driver = {
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.probe = qcom_pcie2_phy_probe,
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.driver = {
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.name = "phy-qcom-pcie2",
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.of_match_table = qcom_pcie2_phy_match_table,
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},
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};
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module_platform_driver(qcom_pcie2_phy_driver);
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MODULE_DESCRIPTION("Qualcomm PCIe PHY driver");
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MODULE_LICENSE("GPL v2");
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