270 lines
7.6 KiB
C
270 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains platform specific structure definitions
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* and init function used by Tiger Lake PCH.
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*
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* Copyright (c) 2022, Intel Corporation.
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* All Rights Reserved.
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*
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*/
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#include "core.h"
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#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
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#define ACPI_GET_LOW_MODE_REGISTERS 1
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const struct pmc_bit_map tgl_pfear_map[] = {
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{"PSF9", BIT(0)},
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{"RES_66", BIT(1)},
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{"RES_67", BIT(2)},
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{"RES_68", BIT(3)},
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{"RES_69", BIT(4)},
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{"RES_70", BIT(5)},
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{"TBTLSX", BIT(6)},
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{}
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};
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const struct pmc_bit_map *ext_tgl_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of tgl_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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tgl_pfear_map,
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NULL
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};
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const struct pmc_bit_map tgl_clocksource_status_map[] = {
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{"USB2PLL_OFF_STS", BIT(18)},
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{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
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{"PCIe_Gen3PLL_OFF_STS", BIT(20)},
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{"OPIOPLL_OFF_STS", BIT(21)},
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{"OCPLL_OFF_STS", BIT(22)},
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{"MainPLL_OFF_STS", BIT(23)},
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{"MIPIPLL_OFF_STS", BIT(24)},
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{"Fast_XTAL_Osc_OFF_STS", BIT(25)},
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{"AC_Ring_Osc_OFF_STS", BIT(26)},
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{"MC_Ring_Osc_OFF_STS", BIT(27)},
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{"SATAPLL_OFF_STS", BIT(29)},
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{"XTAL_USB2PLL_OFF_STS", BIT(31)},
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{}
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};
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const struct pmc_bit_map tgl_power_gating_status_map[] = {
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{"CSME_PG_STS", BIT(0)},
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{"SATA_PG_STS", BIT(1)},
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{"xHCI_PG_STS", BIT(2)},
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{"UFSX2_PG_STS", BIT(3)},
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{"OTG_PG_STS", BIT(5)},
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{"SPA_PG_STS", BIT(6)},
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{"SPB_PG_STS", BIT(7)},
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{"SPC_PG_STS", BIT(8)},
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{"SPD_PG_STS", BIT(9)},
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{"SPE_PG_STS", BIT(10)},
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{"SPF_PG_STS", BIT(11)},
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{"LSX_PG_STS", BIT(13)},
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{"P2SB_PG_STS", BIT(14)},
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{"PSF_PG_STS", BIT(15)},
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{"SBR_PG_STS", BIT(16)},
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{"OPIDMI_PG_STS", BIT(17)},
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{"THC0_PG_STS", BIT(18)},
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{"THC1_PG_STS", BIT(19)},
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{"GBETSN_PG_STS", BIT(20)},
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{"GBE_PG_STS", BIT(21)},
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{"LPSS_PG_STS", BIT(22)},
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{"MMP_UFSX2_PG_STS", BIT(23)},
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{"MMP_UFSX2B_PG_STS", BIT(24)},
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{"FIA_PG_STS", BIT(25)},
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{}
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};
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const struct pmc_bit_map tgl_d3_status_map[] = {
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{"ADSP_D3_STS", BIT(0)},
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{"SATA_D3_STS", BIT(1)},
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{"xHCI0_D3_STS", BIT(2)},
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{"xDCI1_D3_STS", BIT(5)},
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{"SDX_D3_STS", BIT(6)},
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{"EMMC_D3_STS", BIT(7)},
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{"IS_D3_STS", BIT(8)},
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{"THC0_D3_STS", BIT(9)},
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{"THC1_D3_STS", BIT(10)},
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{"GBE_D3_STS", BIT(11)},
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{"GBE_TSN_D3_STS", BIT(12)},
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{}
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};
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const struct pmc_bit_map tgl_vnn_req_status_map[] = {
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{"GPIO_COM0_VNN_REQ_STS", BIT(1)},
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{"GPIO_COM1_VNN_REQ_STS", BIT(2)},
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{"GPIO_COM2_VNN_REQ_STS", BIT(3)},
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{"GPIO_COM3_VNN_REQ_STS", BIT(4)},
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{"GPIO_COM4_VNN_REQ_STS", BIT(5)},
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{"GPIO_COM5_VNN_REQ_STS", BIT(6)},
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{"Audio_VNN_REQ_STS", BIT(7)},
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{"ISH_VNN_REQ_STS", BIT(8)},
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{"CNVI_VNN_REQ_STS", BIT(9)},
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{"eSPI_VNN_REQ_STS", BIT(10)},
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{"Display_VNN_REQ_STS", BIT(11)},
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{"DTS_VNN_REQ_STS", BIT(12)},
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{"SMBUS_VNN_REQ_STS", BIT(14)},
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{"CSME_VNN_REQ_STS", BIT(15)},
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{"SMLINK0_VNN_REQ_STS", BIT(16)},
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{"SMLINK1_VNN_REQ_STS", BIT(17)},
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{"CLINK_VNN_REQ_STS", BIT(20)},
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{"DCI_VNN_REQ_STS", BIT(21)},
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{"ITH_VNN_REQ_STS", BIT(22)},
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{"CSME_VNN_REQ_STS", BIT(24)},
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{"GBE_VNN_REQ_STS", BIT(25)},
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{}
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};
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const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
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{"CPU_C10_REQ_STS_0", BIT(0)},
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{"PCIe_LPM_En_REQ_STS_3", BIT(3)},
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{"ITH_REQ_STS_5", BIT(5)},
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{"CNVI_REQ_STS_6", BIT(6)},
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{"ISH_REQ_STS_7", BIT(7)},
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{"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
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{"PCIe_Clk_REQ_STS_12", BIT(12)},
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{"MPHY_Core_DL_REQ_STS_16", BIT(16)},
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{"Break-even_En_REQ_STS_17", BIT(17)},
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{"Auto-demo_En_REQ_STS_18", BIT(18)},
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{"MPHY_SUS_REQ_STS_22", BIT(22)},
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{"xDCI_attached_REQ_STS_24", BIT(24)},
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{}
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};
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const struct pmc_bit_map tgl_signal_status_map[] = {
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{"LSX_Wake0_En_STS", BIT(0)},
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{"LSX_Wake0_Pol_STS", BIT(1)},
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{"LSX_Wake1_En_STS", BIT(2)},
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{"LSX_Wake1_Pol_STS", BIT(3)},
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{"LSX_Wake2_En_STS", BIT(4)},
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{"LSX_Wake2_Pol_STS", BIT(5)},
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{"LSX_Wake3_En_STS", BIT(6)},
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{"LSX_Wake3_Pol_STS", BIT(7)},
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{"LSX_Wake4_En_STS", BIT(8)},
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{"LSX_Wake4_Pol_STS", BIT(9)},
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{"LSX_Wake5_En_STS", BIT(10)},
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{"LSX_Wake5_Pol_STS", BIT(11)},
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{"LSX_Wake6_En_STS", BIT(12)},
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{"LSX_Wake6_Pol_STS", BIT(13)},
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{"LSX_Wake7_En_STS", BIT(14)},
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{"LSX_Wake7_Pol_STS", BIT(15)},
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{"Intel_Se_IO_Wake0_En_STS", BIT(16)},
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{"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
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{"Intel_Se_IO_Wake1_En_STS", BIT(18)},
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{"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
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{"Int_Timer_SS_Wake0_En_STS", BIT(20)},
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{"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
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{"Int_Timer_SS_Wake1_En_STS", BIT(22)},
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{"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
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{"Int_Timer_SS_Wake2_En_STS", BIT(24)},
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{"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
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{"Int_Timer_SS_Wake3_En_STS", BIT(26)},
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{"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
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{"Int_Timer_SS_Wake4_En_STS", BIT(28)},
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{"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
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{"Int_Timer_SS_Wake5_En_STS", BIT(30)},
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{"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
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{}
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};
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const struct pmc_bit_map *tgl_lpm_maps[] = {
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tgl_clocksource_status_map,
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tgl_power_gating_status_map,
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tgl_d3_status_map,
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tgl_vnn_req_status_map,
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tgl_vnn_misc_status_map,
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tgl_signal_status_map,
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NULL
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};
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const struct pmc_reg_map tgl_reg_map = {
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.pfear_sts = ext_tgl_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
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.lpm_num_maps = TGL_LPM_NUM_MAPS,
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.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
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.lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
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.lpm_en_offset = TGL_LPM_EN_OFFSET,
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.lpm_priority_offset = TGL_LPM_PRI_OFFSET,
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.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
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.lpm_sts = tgl_lpm_maps,
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.lpm_status_offset = TGL_LPM_STATUS_OFFSET,
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.lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
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.etr3_offset = ETR3_OFFSET,
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};
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void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
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{
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struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
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const int num_maps = pmcdev->map->lpm_num_maps;
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u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
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union acpi_object *out_obj;
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struct acpi_device *adev;
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guid_t s0ix_dsm_guid;
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u32 *lpm_req_regs, *addr;
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adev = ACPI_COMPANION(&pdev->dev);
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if (!adev)
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return;
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guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
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out_obj = acpi_evaluate_dsm_typed(adev->handle, &s0ix_dsm_guid, 0,
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ACPI_GET_LOW_MODE_REGISTERS, NULL, ACPI_TYPE_BUFFER);
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if (out_obj) {
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u32 size = out_obj->buffer.length;
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if (size != lpm_size) {
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acpi_handle_debug(adev->handle,
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"_DSM returned unexpected buffer size, have %u, expect %u\n",
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size, lpm_size);
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goto free_acpi_obj;
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}
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} else {
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acpi_handle_debug(adev->handle,
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"_DSM function 0 evaluation failed\n");
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goto free_acpi_obj;
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}
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addr = (u32 *)out_obj->buffer.pointer;
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lpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),
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GFP_KERNEL);
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if (!lpm_req_regs)
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goto free_acpi_obj;
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memcpy(lpm_req_regs, addr, lpm_size);
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pmcdev->lpm_req_regs = lpm_req_regs;
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free_acpi_obj:
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ACPI_FREE(out_obj);
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}
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void tgl_core_configure(struct pmc_dev *pmcdev)
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{
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pmc_core_get_tgl_lpm_reqs(pmcdev->pdev);
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/* Due to a hardware limitation, the GBE LTR blocks PC10
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* when a cable is attached. Tell the PMC to ignore it.
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*/
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dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
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pmc_core_send_ltr_ignore(pmcdev, 3);
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}
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void tgl_core_init(struct pmc_dev *pmcdev)
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{
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pmcdev->map = &tgl_reg_map;
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pmcdev->core_configure = tgl_core_configure;
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}
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