452 lines
12 KiB
C
452 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include "mtk-mmsys.h"
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#include "mt8167-mmsys.h"
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#include "mt8183-mmsys.h"
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#include "mt8186-mmsys.h"
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#include "mt8188-mmsys.h"
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#include "mt8192-mmsys.h"
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#include "mt8195-mmsys.h"
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#include "mt8365-mmsys.h"
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#define MMSYS_SW_RESET_PER_REG 32
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static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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.clk_driver = "clk-mt2701-mm",
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
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.clk_driver = "clk-mt2712-mm",
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
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.clk_driver = "clk-mt6779-mm",
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};
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static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
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.clk_driver = "clk-mt6797-mm",
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};
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static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
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.clk_driver = "clk-mt8167-mm",
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.routes = mt8167_mmsys_routing_table,
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.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
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.clk_driver = "clk-mt8173-mm",
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
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.num_resets = 32,
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};
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static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
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.clk_driver = "clk-mt8183-mm",
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.routes = mmsys_mt8183_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
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.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
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.num_resets = 32,
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};
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static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
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.clk_driver = "clk-mt8186-mm",
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.routes = mmsys_mt8186_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
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.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
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.num_resets = 32,
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};
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static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
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.clk_driver = "clk-mt8188-vdo0",
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.routes = mmsys_mt8188_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
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.clk_driver = "clk-mt8192-mm",
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.routes = mmsys_mt8192_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
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.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
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.num_resets = 32,
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};
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static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
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.clk_driver = "clk-mt8195-vdo0",
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.routes = mmsys_mt8195_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
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.clk_driver = "clk-mt8195-vdo1",
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.routes = mmsys_mt8195_vdo1_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
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.sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
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.num_resets = 64,
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};
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static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
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.clk_driver = "clk-mt8195-vpp0",
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.is_vppsys = true,
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};
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static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
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.clk_driver = "clk-mt8195-vpp1",
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.is_vppsys = true,
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};
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static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
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.clk_driver = "clk-mt8365-mm",
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.routes = mt8365_mmsys_routing_table,
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.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
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};
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struct mtk_mmsys {
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void __iomem *regs;
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const struct mtk_mmsys_driver_data *data;
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spinlock_t lock; /* protects mmsys_sw_rst_b reg */
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struct reset_controller_dev rcdev;
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struct cmdq_client_reg cmdq_base;
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};
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static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
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struct cmdq_pkt *cmdq_pkt)
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{
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u32 tmp;
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (cmdq_pkt) {
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if (mmsys->cmdq_base.size == 0) {
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pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq");
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return;
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}
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cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
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mmsys->cmdq_base.offset + offset, val,
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mask);
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return;
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}
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#endif
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tmp = readl_relaxed(mmsys->regs + offset);
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tmp = (tmp & ~mask) | (val & mask);
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writel_relaxed(tmp, mmsys->regs + offset);
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}
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void mtk_mmsys_ddp_connect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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const struct mtk_mmsys_routes *routes = mmsys->data->routes;
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int i;
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for (i = 0; i < mmsys->data->num_routes; i++)
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if (cur == routes[i].from_comp && next == routes[i].to_comp)
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mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
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routes[i].val, NULL);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
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void mtk_mmsys_ddp_disconnect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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const struct mtk_mmsys_routes *routes = mmsys->data->routes;
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int i;
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for (i = 0; i < mmsys->data->num_routes; i++)
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if (cur == routes[i].from_comp && next == routes[i].to_comp)
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mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
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void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height,
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struct cmdq_pkt *cmdq_pkt)
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{
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mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
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~0, height << 16 | width, cmdq_pkt);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
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void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
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struct cmdq_pkt *cmdq_pkt)
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{
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mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
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be_height << 16 | be_width, cmdq_pkt);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
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void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
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u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
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alpha << 16 | alpha, cmdq_pkt);
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mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
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alpha_sel << (19 + idx), cmdq_pkt);
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mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
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GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
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void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
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struct cmdq_pkt *cmdq_pkt)
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{
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mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
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BIT(4), channel_swap << 4, cmdq_pkt);
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
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void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
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{
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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switch (val) {
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case MTK_DPI_RGB888_SDR_CON:
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mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
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MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL);
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break;
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case MTK_DPI_RGB565_SDR_CON:
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mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
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MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL);
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break;
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case MTK_DPI_RGB565_DDR_CON:
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mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
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MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL);
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break;
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case MTK_DPI_RGB888_DDR_CON:
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default:
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mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
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MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL);
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break;
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}
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
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static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
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bool assert)
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{
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struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
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unsigned long flags;
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u32 offset;
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u32 reg;
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offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
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id = id % MMSYS_SW_RESET_PER_REG;
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reg = mmsys->data->sw0_rst_offset + offset;
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spin_lock_irqsave(&mmsys->lock, flags);
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if (assert)
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mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
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else
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mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
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spin_unlock_irqrestore(&mmsys->lock, flags);
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return 0;
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}
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static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, true);
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}
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static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, false);
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}
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static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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int ret;
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ret = mtk_mmsys_reset_assert(rcdev, id);
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if (ret)
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return ret;
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usleep_range(1000, 1100);
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return mtk_mmsys_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops mtk_mmsys_reset_ops = {
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.assert = mtk_mmsys_reset_assert,
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.deassert = mtk_mmsys_reset_deassert,
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.reset = mtk_mmsys_reset,
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};
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static int mtk_mmsys_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct platform_device *clks;
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struct platform_device *drm;
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struct mtk_mmsys *mmsys;
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int ret;
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mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
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if (!mmsys)
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return -ENOMEM;
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mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mmsys->regs)) {
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ret = PTR_ERR(mmsys->regs);
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dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
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return ret;
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}
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mmsys->data = of_device_get_match_data(&pdev->dev);
|
||
|
|
|
||
|
|
if (mmsys->data->num_resets > 0) {
|
||
|
|
spin_lock_init(&mmsys->lock);
|
||
|
|
|
||
|
|
mmsys->rcdev.owner = THIS_MODULE;
|
||
|
|
mmsys->rcdev.nr_resets = mmsys->data->num_resets;
|
||
|
|
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
|
||
|
|
mmsys->rcdev.of_node = pdev->dev.of_node;
|
||
|
|
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
||
|
|
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
|
||
|
|
if (ret)
|
||
|
|
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
|
||
|
|
#endif
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, mmsys);
|
||
|
|
|
||
|
|
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
|
||
|
|
PLATFORM_DEVID_AUTO, NULL, 0);
|
||
|
|
if (IS_ERR(clks))
|
||
|
|
return PTR_ERR(clks);
|
||
|
|
|
||
|
|
if (mmsys->data->is_vppsys)
|
||
|
|
goto out_probe_done;
|
||
|
|
|
||
|
|
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
|
||
|
|
PLATFORM_DEVID_AUTO, NULL, 0);
|
||
|
|
if (IS_ERR(drm)) {
|
||
|
|
platform_device_unregister(clks);
|
||
|
|
return PTR_ERR(drm);
|
||
|
|
}
|
||
|
|
|
||
|
|
out_probe_done:
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id of_match_mtk_mmsys[] = {
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt2701-mmsys",
|
||
|
|
.data = &mt2701_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt2712-mmsys",
|
||
|
|
.data = &mt2712_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt6779-mmsys",
|
||
|
|
.data = &mt6779_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt6797-mmsys",
|
||
|
|
.data = &mt6797_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8167-mmsys",
|
||
|
|
.data = &mt8167_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8173-mmsys",
|
||
|
|
.data = &mt8173_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8183-mmsys",
|
||
|
|
.data = &mt8183_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8186-mmsys",
|
||
|
|
.data = &mt8186_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8188-vdosys0",
|
||
|
|
.data = &mt8188_vdosys0_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8192-mmsys",
|
||
|
|
.data = &mt8192_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{ /* deprecated compatible */
|
||
|
|
.compatible = "mediatek,mt8195-mmsys",
|
||
|
|
.data = &mt8195_vdosys0_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8195-vdosys0",
|
||
|
|
.data = &mt8195_vdosys0_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8195-vdosys1",
|
||
|
|
.data = &mt8195_vdosys1_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8195-vppsys0",
|
||
|
|
.data = &mt8195_vppsys0_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8195-vppsys1",
|
||
|
|
.data = &mt8195_vppsys1_driver_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "mediatek,mt8365-mmsys",
|
||
|
|
.data = &mt8365_mmsys_driver_data,
|
||
|
|
},
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver mtk_mmsys_drv = {
|
||
|
|
.driver = {
|
||
|
|
.name = "mtk-mmsys",
|
||
|
|
.of_match_table = of_match_mtk_mmsys,
|
||
|
|
},
|
||
|
|
.probe = mtk_mmsys_probe,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init mtk_mmsys_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&mtk_mmsys_drv);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit mtk_mmsys_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&mtk_mmsys_drv);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(mtk_mmsys_init);
|
||
|
|
module_exit(mtk_mmsys_exit);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
|
||
|
|
MODULE_DESCRIPTION("MediaTek SoC MMSYS driver");
|
||
|
|
MODULE_LICENSE("GPL");
|