98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*****************************************************************************
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*
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* Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
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* Jean-Christian Hassler <jhassler@free.fr>
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* Copyright 1998 Emagic Soft- und Hardware GmbH
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* Copyright 2002 Martijn Sipkema
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*
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* This file is part of the Audiowerk2 ALSA driver
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*
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*****************************************************************************/
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#define TSL_WS0 (1UL << 31)
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#define TSL_WS1 (1UL << 30)
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#define TSL_WS2 (1UL << 29)
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#define TSL_WS3 (1UL << 28)
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#define TSL_WS4 (1UL << 27)
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#define TSL_DIS_A1 (1UL << 24)
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#define TSL_SDW_A1 (1UL << 23)
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#define TSL_SIB_A1 (1UL << 22)
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#define TSL_SF_A1 (1UL << 21)
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#define TSL_LF_A1 (1UL << 20)
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#define TSL_BSEL_A1 (1UL << 17)
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#define TSL_DOD_A1 (1UL << 15)
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#define TSL_LOW_A1 (1UL << 14)
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#define TSL_DIS_A2 (1UL << 11)
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#define TSL_SDW_A2 (1UL << 10)
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#define TSL_SIB_A2 (1UL << 9)
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#define TSL_SF_A2 (1UL << 8)
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#define TSL_LF_A2 (1UL << 7)
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#define TSL_BSEL_A2 (1UL << 4)
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#define TSL_DOD_A2 (1UL << 2)
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#define TSL_LOW_A2 (1UL << 1)
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#define TSL_EOS (1UL << 0)
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/* Audiowerk8 hardware setup: */
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/* WS0, SD4, TSL1 - Analog/ digital in */
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/* WS1, SD0, TSL1 - Analog out #1, digital out */
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/* WS2, SD2, TSL1 - Analog out #2 */
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/* WS3, SD1, TSL2 - Analog out #3 */
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/* WS4, SD3, TSL2 - Analog out #4 */
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/* Audiowerk8 timing: */
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/* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
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/* A1_INPUT: */
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/* SD4: <_ADC-L_>-------<_ADC-R_>-------< */
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/* WS0: _______________/---------------\_ */
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/* A1_OUTPUT: */
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/* SD0: <_1-L___>-------<_1-R___>-------< */
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/* WS1: _______________/---------------\_ */
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/* SD2: >-------<_2-L___>-------<_2-R___> */
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/* WS2: -------\_______________/--------- */
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/* A2_OUTPUT: */
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/* SD1: <_3-L___>-------<_3-R___>-------< */
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/* WS3: _______________/---------------\_ */
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/* SD3: >-------<_4-L___>-------<_4-R___> */
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/* WS4: -------\_______________/--------- */
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static const int tsl1[8] = {
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1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
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1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
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0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
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0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
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1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
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1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
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0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
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0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
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0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
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0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
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};
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static const int tsl2[8] = {
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0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
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0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
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0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
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0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
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0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
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0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
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0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
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0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
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};
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