431 lines
9.5 KiB
C
431 lines
9.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright(c) 2015-17 Intel Corporation
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/*
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* skl-ssp-clk.c - ASoC skylake ssp clock driver
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <sound/intel-nhlt.h>
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#include "skl.h"
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#include "skl-ssp-clk.h"
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#include "skl-topology.h"
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#define to_skl_clk(_hw) container_of(_hw, struct skl_clk, hw)
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struct skl_clk_parent {
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struct clk_hw *hw;
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struct clk_lookup *lookup;
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};
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struct skl_clk {
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struct clk_hw hw;
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struct clk_lookup *lookup;
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unsigned long rate;
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struct skl_clk_pdata *pdata;
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u32 id;
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};
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struct skl_clk_data {
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struct skl_clk_parent parent[SKL_MAX_CLK_SRC];
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struct skl_clk *clk[SKL_MAX_CLK_CNT];
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u8 avail_clk_cnt;
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};
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static int skl_get_clk_type(u32 index)
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{
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switch (index) {
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case 0 ... (SKL_SCLK_OFS - 1):
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return SKL_MCLK;
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case SKL_SCLK_OFS ... (SKL_SCLKFS_OFS - 1):
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return SKL_SCLK;
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case SKL_SCLKFS_OFS ... (SKL_MAX_CLK_CNT - 1):
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return SKL_SCLK_FS;
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default:
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return -EINVAL;
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}
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}
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static int skl_get_vbus_id(u32 index, u8 clk_type)
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{
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switch (clk_type) {
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case SKL_MCLK:
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return index;
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case SKL_SCLK:
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return index - SKL_SCLK_OFS;
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case SKL_SCLK_FS:
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return index - SKL_SCLKFS_OFS;
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default:
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return -EINVAL;
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}
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}
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static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type)
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{
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struct nhlt_fmt_cfg *fmt_cfg;
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union skl_clk_ctrl_ipc *ipc;
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struct wav_fmt *wfmt;
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if (!rcfg)
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return;
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ipc = &rcfg->dma_ctl_ipc;
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if (clk_type == SKL_SCLK_FS) {
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fmt_cfg = (struct nhlt_fmt_cfg *)rcfg->config;
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wfmt = &fmt_cfg->fmt_ext.fmt;
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/* Remove TLV Header size */
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ipc->sclk_fs.hdr.size = sizeof(struct skl_dmactrl_sclkfs_cfg) -
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sizeof(struct skl_tlv_hdr);
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ipc->sclk_fs.sampling_frequency = wfmt->samples_per_sec;
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ipc->sclk_fs.bit_depth = wfmt->bits_per_sample;
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ipc->sclk_fs.valid_bit_depth =
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fmt_cfg->fmt_ext.sample.valid_bits_per_sample;
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ipc->sclk_fs.number_of_channels = wfmt->channels;
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} else {
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ipc->mclk.hdr.type = DMA_CLK_CONTROLS;
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/* Remove TLV Header size */
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ipc->mclk.hdr.size = sizeof(struct skl_dmactrl_mclk_cfg) -
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sizeof(struct skl_tlv_hdr);
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}
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}
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/* Sends dma control IPC to turn the clock ON/OFF */
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static int skl_send_clk_dma_control(struct skl_dev *skl,
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struct skl_clk_rate_cfg_table *rcfg,
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u32 vbus_id, u8 clk_type,
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bool enable)
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{
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struct nhlt_specific_cfg *sp_cfg;
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u32 i2s_config_size, node_id = 0;
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struct nhlt_fmt_cfg *fmt_cfg;
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union skl_clk_ctrl_ipc *ipc;
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void *i2s_config = NULL;
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u8 *data, size;
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int ret;
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if (!rcfg)
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return -EIO;
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ipc = &rcfg->dma_ctl_ipc;
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fmt_cfg = (struct nhlt_fmt_cfg *)rcfg->config;
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sp_cfg = &fmt_cfg->config;
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if (clk_type == SKL_SCLK_FS) {
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ipc->sclk_fs.hdr.type =
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enable ? DMA_TRANSMITION_START : DMA_TRANSMITION_STOP;
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data = (u8 *)&ipc->sclk_fs;
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size = sizeof(struct skl_dmactrl_sclkfs_cfg);
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} else {
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/* 1 to enable mclk, 0 to enable sclk */
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if (clk_type == SKL_SCLK)
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ipc->mclk.mclk = 0;
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else
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ipc->mclk.mclk = 1;
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ipc->mclk.keep_running = enable;
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ipc->mclk.warm_up_over = enable;
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ipc->mclk.clk_stop_over = !enable;
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data = (u8 *)&ipc->mclk;
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size = sizeof(struct skl_dmactrl_mclk_cfg);
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}
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i2s_config_size = sp_cfg->size + size;
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i2s_config = kzalloc(i2s_config_size, GFP_KERNEL);
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if (!i2s_config)
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return -ENOMEM;
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/* copy blob */
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memcpy(i2s_config, sp_cfg->caps, sp_cfg->size);
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/* copy additional dma controls information */
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memcpy(i2s_config + sp_cfg->size, data, size);
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node_id = ((SKL_DMA_I2S_LINK_INPUT_CLASS << 8) | (vbus_id << 4));
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ret = skl_dsp_set_dma_control(skl, (u32 *)i2s_config,
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i2s_config_size, node_id);
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kfree(i2s_config);
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return ret;
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}
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static struct skl_clk_rate_cfg_table *skl_get_rate_cfg(
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struct skl_clk_rate_cfg_table *rcfg,
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unsigned long rate)
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{
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int i;
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for (i = 0; (i < SKL_MAX_CLK_RATES) && rcfg[i].rate; i++) {
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if (rcfg[i].rate == rate)
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return &rcfg[i];
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}
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return NULL;
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}
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static int skl_clk_change_status(struct skl_clk *clkdev,
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bool enable)
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{
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struct skl_clk_rate_cfg_table *rcfg;
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int vbus_id, clk_type;
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clk_type = skl_get_clk_type(clkdev->id);
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if (clk_type < 0)
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return clk_type;
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vbus_id = skl_get_vbus_id(clkdev->id, clk_type);
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if (vbus_id < 0)
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return vbus_id;
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rcfg = skl_get_rate_cfg(clkdev->pdata->ssp_clks[clkdev->id].rate_cfg,
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clkdev->rate);
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if (!rcfg)
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return -EINVAL;
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return skl_send_clk_dma_control(clkdev->pdata->pvt_data, rcfg,
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vbus_id, clk_type, enable);
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}
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static int skl_clk_prepare(struct clk_hw *hw)
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{
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struct skl_clk *clkdev = to_skl_clk(hw);
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return skl_clk_change_status(clkdev, true);
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}
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static void skl_clk_unprepare(struct clk_hw *hw)
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{
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struct skl_clk *clkdev = to_skl_clk(hw);
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skl_clk_change_status(clkdev, false);
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}
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static int skl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct skl_clk *clkdev = to_skl_clk(hw);
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struct skl_clk_rate_cfg_table *rcfg;
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int clk_type;
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if (!rate)
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return -EINVAL;
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rcfg = skl_get_rate_cfg(clkdev->pdata->ssp_clks[clkdev->id].rate_cfg,
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rate);
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if (!rcfg)
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return -EINVAL;
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clk_type = skl_get_clk_type(clkdev->id);
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if (clk_type < 0)
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return clk_type;
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skl_fill_clk_ipc(rcfg, clk_type);
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clkdev->rate = rate;
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return 0;
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}
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static unsigned long skl_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct skl_clk *clkdev = to_skl_clk(hw);
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if (clkdev->rate)
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return clkdev->rate;
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return 0;
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}
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/* Not supported by clk driver. Implemented to satisfy clk fw */
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static long skl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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/*
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* prepare/unprepare are used instead of enable/disable as IPC will be sent
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* in non-atomic context.
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*/
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static const struct clk_ops skl_clk_ops = {
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.prepare = skl_clk_prepare,
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.unprepare = skl_clk_unprepare,
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.set_rate = skl_clk_set_rate,
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.round_rate = skl_clk_round_rate,
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.recalc_rate = skl_clk_recalc_rate,
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};
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static void unregister_parent_src_clk(struct skl_clk_parent *pclk,
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unsigned int id)
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{
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while (id--) {
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clkdev_drop(pclk[id].lookup);
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clk_hw_unregister_fixed_rate(pclk[id].hw);
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}
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}
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static void unregister_src_clk(struct skl_clk_data *dclk)
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{
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while (dclk->avail_clk_cnt--)
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clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup);
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}
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static int skl_register_parent_clks(struct device *dev,
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struct skl_clk_parent *parent,
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struct skl_clk_parent_src *pclk)
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{
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int i, ret;
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for (i = 0; i < SKL_MAX_CLK_SRC; i++) {
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/* Register Parent clock */
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parent[i].hw = clk_hw_register_fixed_rate(dev, pclk[i].name,
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pclk[i].parent_name, 0, pclk[i].rate);
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if (IS_ERR(parent[i].hw)) {
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ret = PTR_ERR(parent[i].hw);
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goto err;
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}
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parent[i].lookup = clkdev_hw_create(parent[i].hw, pclk[i].name,
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NULL);
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if (!parent[i].lookup) {
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clk_hw_unregister_fixed_rate(parent[i].hw);
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ret = -ENOMEM;
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goto err;
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}
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}
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return 0;
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err:
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unregister_parent_src_clk(parent, i);
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return ret;
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}
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/* Assign fmt_config to clk_data */
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static struct skl_clk *register_skl_clk(struct device *dev,
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struct skl_ssp_clk *clk,
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struct skl_clk_pdata *clk_pdata, int id)
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{
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struct clk_init_data init;
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struct skl_clk *clkdev;
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int ret;
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clkdev = devm_kzalloc(dev, sizeof(*clkdev), GFP_KERNEL);
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if (!clkdev)
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return ERR_PTR(-ENOMEM);
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init.name = clk->name;
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init.ops = &skl_clk_ops;
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init.flags = CLK_SET_RATE_GATE;
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init.parent_names = &clk->parent_name;
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init.num_parents = 1;
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clkdev->hw.init = &init;
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clkdev->pdata = clk_pdata;
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clkdev->id = id;
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ret = devm_clk_hw_register(dev, &clkdev->hw);
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if (ret) {
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clkdev = ERR_PTR(ret);
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return clkdev;
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}
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clkdev->lookup = clkdev_hw_create(&clkdev->hw, init.name, NULL);
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if (!clkdev->lookup)
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clkdev = ERR_PTR(-ENOMEM);
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return clkdev;
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}
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static int skl_clk_dev_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device *parent_dev = dev->parent;
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struct skl_clk_parent_src *parent_clks;
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struct skl_clk_pdata *clk_pdata;
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struct skl_clk_data *data;
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struct skl_ssp_clk *clks;
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int ret, i;
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clk_pdata = dev_get_platdata(&pdev->dev);
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parent_clks = clk_pdata->parent_clks;
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clks = clk_pdata->ssp_clks;
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if (!parent_clks || !clks)
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return -EIO;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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/* Register Parent clock */
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ret = skl_register_parent_clks(parent_dev, data->parent, parent_clks);
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if (ret < 0)
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return ret;
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|
|
||
|
|
for (i = 0; i < clk_pdata->num_clks; i++) {
|
||
|
|
/*
|
||
|
|
* Only register valid clocks
|
||
|
|
* i.e. for which nhlt entry is present.
|
||
|
|
*/
|
||
|
|
if (clks[i].rate_cfg[0].rate == 0)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
data->clk[data->avail_clk_cnt] = register_skl_clk(dev,
|
||
|
|
&clks[i], clk_pdata, i);
|
||
|
|
|
||
|
|
if (IS_ERR(data->clk[data->avail_clk_cnt])) {
|
||
|
|
ret = PTR_ERR(data->clk[data->avail_clk_cnt]);
|
||
|
|
goto err_unreg_skl_clk;
|
||
|
|
}
|
||
|
|
|
||
|
|
data->avail_clk_cnt++;
|
||
|
|
}
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, data);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_unreg_skl_clk:
|
||
|
|
unregister_src_clk(data);
|
||
|
|
unregister_parent_src_clk(data->parent, SKL_MAX_CLK_SRC);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int skl_clk_dev_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct skl_clk_data *data;
|
||
|
|
|
||
|
|
data = platform_get_drvdata(pdev);
|
||
|
|
unregister_src_clk(data);
|
||
|
|
unregister_parent_src_clk(data->parent, SKL_MAX_CLK_SRC);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver skl_clk_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "skl-ssp-clk",
|
||
|
|
},
|
||
|
|
.probe = skl_clk_dev_probe,
|
||
|
|
.remove = skl_clk_dev_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(skl_clk_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Skylake clock driver");
|
||
|
|
MODULE_AUTHOR("Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>");
|
||
|
|
MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_ALIAS("platform:skl-ssp-clk");
|