507 lines
14 KiB
C
507 lines
14 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Cannonlake.
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*/
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#include <sound/sof/ext_manifest4.h>
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#include <sound/sof/ipc4/header.h>
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#include <trace/events/sof_intel.h>
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#include "../ipc4-priv.h"
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
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irqreturn_t cnl_ipc4_irq_thread(int irq, void *context)
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{
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struct sof_ipc4_msg notification_data = {{ 0 }};
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struct snd_sof_dev *sdev = context;
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bool ack_received = false;
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bool ipc_irq = false;
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u32 hipcida, hipctdr;
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
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/* DSP received the message */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE, 0);
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cnl_ipc_dsp_done(sdev);
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ipc_irq = true;
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ack_received = true;
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}
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if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
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/* Message from DSP (reply or notification) */
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u32 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDD);
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u32 primary = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
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u32 extension = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
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if (primary & SOF_IPC4_MSG_DIR_MASK) {
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/* Reply received */
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if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
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struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
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data->primary = primary;
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data->extension = extension;
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spin_lock_irq(&sdev->ipc_lock);
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snd_sof_ipc_get_reply(sdev);
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cnl_ipc_host_done(sdev);
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snd_sof_ipc_reply(sdev, data->primary);
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spin_unlock_irq(&sdev->ipc_lock);
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} else {
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dev_dbg_ratelimited(sdev->dev,
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"IPC reply before FW_READY: %#x|%#x\n",
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primary, extension);
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}
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} else {
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/* Notification received */
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notification_data.primary = primary;
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notification_data.extension = extension;
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sdev->ipc->msg.rx_data = ¬ification_data;
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snd_sof_ipc_msgs_rx(sdev);
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sdev->ipc->msg.rx_data = NULL;
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/* Let DSP know that we have finished processing the message */
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cnl_ipc_host_done(sdev);
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}
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ipc_irq = true;
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}
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if (!ipc_irq)
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/* This interrupt is not shared so no need to return IRQ_NONE. */
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dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
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if (ack_received) {
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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if (hdev->delayed_ipc_tx_msg)
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cnl_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg);
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}
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return IRQ_HANDLED;
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}
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irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 hipci;
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u32 hipcida;
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u32 hipctdr;
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u32 hipctdd;
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u32 msg;
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u32 msg_ext;
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bool ipc_irq = false;
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
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hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
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/* reply message from DSP */
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if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
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msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
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msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
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trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
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/* mask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE, 0);
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if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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hda_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, msg);
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cnl_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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} else {
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dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
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msg);
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}
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ipc_irq = true;
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}
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/* new message from DSP */
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if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
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msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
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msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
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trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
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/* handle messages from DSP */
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if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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bool non_recoverable = true;
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/*
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* This is a PANIC message!
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*
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* If it is arriving during firmware boot and it is not
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* the last boot attempt then change the non_recoverable
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* to false as the DSP might be able to boot in the next
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* iteration(s)
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*/
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if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
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hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS)
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non_recoverable = false;
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snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
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non_recoverable);
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} else {
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snd_sof_ipc_msgs_rx(sdev);
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}
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cnl_ipc_host_done(sdev);
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ipc_irq = true;
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}
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if (!ipc_irq) {
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/*
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* This interrupt is not shared so no need to return IRQ_NONE.
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*/
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dev_dbg_ratelimited(sdev->dev,
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"nothing to do in IPC IRQ thread\n");
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}
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return IRQ_HANDLED;
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}
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
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{
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/*
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* clear busy interrupt to tell dsp controller this
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* interrupt has been accepted, not trigger it again
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDR,
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CNL_DSP_REG_HIPCTDR_BUSY,
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CNL_DSP_REG_HIPCTDR_BUSY);
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/*
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* set done bit to ack dsp the msg has been
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* processed and send reply msg to dsp
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDA,
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CNL_DSP_REG_HIPCTDA_DONE,
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CNL_DSP_REG_HIPCTDA_DONE);
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}
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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/*
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* set DONE bit - tell DSP we have received the reply msg
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* from DSP, and processed it, don't send more reply to host
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCIDA,
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CNL_DSP_REG_HIPCIDA_DONE,
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CNL_DSP_REG_HIPCIDA_DONE);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE,
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CNL_DSP_REG_HIPCCTL_DONE);
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}
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static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
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u32 *dr, u32 *dd)
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{
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struct sof_ipc_pm_gate *pm_gate = msg->msg_data;
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if (pm_gate->hdr.cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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/* send the compact message via the primary register */
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*dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
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/* send payload via the extended data register */
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*dd = pm_gate->flags;
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return true;
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}
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return false;
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}
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int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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struct sof_ipc4_msg *msg_data = msg->msg_data;
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if (hda_ipc4_tx_is_busy(sdev)) {
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hdev->delayed_ipc_tx_msg = msg;
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return 0;
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}
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hdev->delayed_ipc_tx_msg = NULL;
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/* send the message via mailbox */
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if (msg_data->data_size)
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sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
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msg_data->data_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, msg_data->extension);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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msg_data->primary | CNL_DSP_REG_HIPCIDR_BUSY);
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hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
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return 0;
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}
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int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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struct sof_ipc_cmd_hdr *hdr;
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u32 dr = 0;
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u32 dd = 0;
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/*
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* Currently the only compact IPC supported is the PM_GATE
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* IPC which is used for transitioning the DSP between the
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* D0I0 and D0I3 states. And these are sent only during the
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* set_power_state() op. Therefore, there will never be a case
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* that a compact IPC results in the DSP exiting D0I3 without
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* the host and FW being in sync.
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*/
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if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
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/* send the message via IPC registers */
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
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dd);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY | dr);
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return 0;
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}
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/* send the message via mailbox */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY);
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hdr = msg->msg_data;
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/*
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* Use mod_delayed_work() to schedule the delayed work
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* to avoid scheduling multiple workqueue items when
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* IPCs are sent at a high-rate. mod_delayed_work()
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* modifies the timer if the work is pending.
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* Also, a new delayed work should not be queued after the
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* CTX_SAVE IPC, which is sent before the DSP enters D3.
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*/
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if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
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mod_delayed_work(system_wq, &hdev->d0i3_work,
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msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void cnl_ipc_dump(struct snd_sof_dev *sdev)
|
||
|
|
{
|
||
|
|
u32 hipcctl;
|
||
|
|
u32 hipcida;
|
||
|
|
u32 hipctdr;
|
||
|
|
|
||
|
|
hda_ipc_irq_dump(sdev);
|
||
|
|
|
||
|
|
/* read IPC status */
|
||
|
|
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
|
||
|
|
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
|
||
|
|
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
|
||
|
|
|
||
|
|
/* dump the IPC regs */
|
||
|
|
/* TODO: parse the raw msg */
|
||
|
|
dev_err(sdev->dev,
|
||
|
|
"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
|
||
|
|
hipcida, hipctdr, hipcctl);
|
||
|
|
}
|
||
|
|
|
||
|
|
void cnl_ipc4_dump(struct snd_sof_dev *sdev)
|
||
|
|
{
|
||
|
|
u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
|
||
|
|
|
||
|
|
hda_ipc_irq_dump(sdev);
|
||
|
|
|
||
|
|
hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
|
||
|
|
hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD);
|
||
|
|
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
|
||
|
|
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
|
||
|
|
hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
|
||
|
|
hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDA);
|
||
|
|
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
|
||
|
|
|
||
|
|
/* dump the IPC regs */
|
||
|
|
/* TODO: parse the raw msg */
|
||
|
|
dev_err(sdev->dev,
|
||
|
|
"Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
|
||
|
|
hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* cannonlake ops */
|
||
|
|
struct snd_sof_dsp_ops sof_cnl_ops;
|
||
|
|
EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||
|
|
|
||
|
|
int sof_cnl_ops_init(struct snd_sof_dev *sdev)
|
||
|
|
{
|
||
|
|
/* common defaults */
|
||
|
|
memcpy(&sof_cnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
|
||
|
|
|
||
|
|
/* probe/remove/shutdown */
|
||
|
|
sof_cnl_ops.shutdown = hda_dsp_shutdown;
|
||
|
|
|
||
|
|
/* ipc */
|
||
|
|
if (sdev->pdata->ipc_type == SOF_IPC) {
|
||
|
|
/* doorbell */
|
||
|
|
sof_cnl_ops.irq_thread = cnl_ipc_irq_thread;
|
||
|
|
|
||
|
|
/* ipc */
|
||
|
|
sof_cnl_ops.send_msg = cnl_ipc_send_msg;
|
||
|
|
|
||
|
|
/* debug */
|
||
|
|
sof_cnl_ops.ipc_dump = cnl_ipc_dump;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
|
||
|
|
struct sof_ipc4_fw_data *ipc4_data;
|
||
|
|
|
||
|
|
sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
|
||
|
|
if (!sdev->private)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
ipc4_data = sdev->private;
|
||
|
|
ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
|
||
|
|
|
||
|
|
ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_8;
|
||
|
|
|
||
|
|
/* External library loading support */
|
||
|
|
ipc4_data->load_library = hda_dsp_ipc4_load_library;
|
||
|
|
|
||
|
|
/* doorbell */
|
||
|
|
sof_cnl_ops.irq_thread = cnl_ipc4_irq_thread;
|
||
|
|
|
||
|
|
/* ipc */
|
||
|
|
sof_cnl_ops.send_msg = cnl_ipc4_send_msg;
|
||
|
|
|
||
|
|
/* debug */
|
||
|
|
sof_cnl_ops.ipc_dump = cnl_ipc4_dump;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* set DAI driver ops */
|
||
|
|
hda_set_dai_drv_ops(sdev, &sof_cnl_ops);
|
||
|
|
|
||
|
|
/* debug */
|
||
|
|
sof_cnl_ops.debug_map = cnl_dsp_debugfs;
|
||
|
|
sof_cnl_ops.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs);
|
||
|
|
|
||
|
|
/* pre/post fw run */
|
||
|
|
sof_cnl_ops.post_fw_run = hda_dsp_post_fw_run;
|
||
|
|
|
||
|
|
/* firmware run */
|
||
|
|
sof_cnl_ops.run = hda_dsp_cl_boot_firmware;
|
||
|
|
|
||
|
|
/* dsp core get/put */
|
||
|
|
sof_cnl_ops.core_get = hda_dsp_core_get;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS(sof_cnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||
|
|
|
||
|
|
const struct sof_intel_dsp_desc cnl_chip_info = {
|
||
|
|
/* Cannonlake */
|
||
|
|
.cores_num = 4,
|
||
|
|
.init_core_mask = 1,
|
||
|
|
.host_managed_cores_mask = GENMASK(3, 0),
|
||
|
|
.ipc_req = CNL_DSP_REG_HIPCIDR,
|
||
|
|
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
|
||
|
|
.ipc_ack = CNL_DSP_REG_HIPCIDA,
|
||
|
|
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
|
||
|
|
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
|
||
|
|
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
|
||
|
|
.rom_init_timeout = 300,
|
||
|
|
.ssp_count = CNL_SSP_COUNT,
|
||
|
|
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||
|
|
.sdw_shim_base = SDW_SHIM_BASE,
|
||
|
|
.sdw_alh_base = SDW_ALH_BASE,
|
||
|
|
.d0i3_offset = SOF_HDA_VS_D0I3C,
|
||
|
|
.read_sdw_lcount = hda_sdw_check_lcount_common,
|
||
|
|
.enable_sdw_irq = hda_common_enable_sdw_irq,
|
||
|
|
.check_sdw_irq = hda_common_check_sdw_irq,
|
||
|
|
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||
|
|
.cl_init = cl_dsp_init,
|
||
|
|
.power_down_dsp = hda_power_down_dsp,
|
||
|
|
.disable_interrupts = hda_dsp_disable_interrupts,
|
||
|
|
.hw_ip_version = SOF_INTEL_CAVS_1_8,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* JasperLake is technically derived from IceLake, and should be in
|
||
|
|
* described in icl.c. However since JasperLake was designed with
|
||
|
|
* two cores, it cannot support the IceLake-specific power-up sequences
|
||
|
|
* which rely on core3. To simplify, JasperLake uses the CannonLake ops and
|
||
|
|
* is described in cnl.c
|
||
|
|
*/
|
||
|
|
const struct sof_intel_dsp_desc jsl_chip_info = {
|
||
|
|
/* Jasperlake */
|
||
|
|
.cores_num = 2,
|
||
|
|
.init_core_mask = 1,
|
||
|
|
.host_managed_cores_mask = GENMASK(1, 0),
|
||
|
|
.ipc_req = CNL_DSP_REG_HIPCIDR,
|
||
|
|
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
|
||
|
|
.ipc_ack = CNL_DSP_REG_HIPCIDA,
|
||
|
|
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
|
||
|
|
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
|
||
|
|
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
|
||
|
|
.rom_init_timeout = 300,
|
||
|
|
.ssp_count = ICL_SSP_COUNT,
|
||
|
|
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||
|
|
.sdw_shim_base = SDW_SHIM_BASE,
|
||
|
|
.sdw_alh_base = SDW_ALH_BASE,
|
||
|
|
.d0i3_offset = SOF_HDA_VS_D0I3C,
|
||
|
|
.read_sdw_lcount = hda_sdw_check_lcount_common,
|
||
|
|
.enable_sdw_irq = hda_common_enable_sdw_irq,
|
||
|
|
.check_sdw_irq = hda_common_check_sdw_irq,
|
||
|
|
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||
|
|
.cl_init = cl_dsp_init,
|
||
|
|
.power_down_dsp = hda_power_down_dsp,
|
||
|
|
.disable_interrupts = hda_dsp_disable_interrupts,
|
||
|
|
.hw_ip_version = SOF_INTEL_CAVS_2_0,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|