57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_peq.h - Definitions for Tegra210 PEQ driver
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*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_PEQ_H__
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#define __TEGRA210_PEQ_H__
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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/* Register offsets from PEQ base */
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#define TEGRA210_PEQ_SOFT_RESET 0x0
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#define TEGRA210_PEQ_CG 0x4
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#define TEGRA210_PEQ_STATUS 0x8
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#define TEGRA210_PEQ_CFG 0xc
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#define TEGRA210_PEQ_CFG_RAM_CTRL 0x10
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#define TEGRA210_PEQ_CFG_RAM_DATA 0x14
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#define TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL 0x18
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#define TEGRA210_PEQ_CFG_RAM_SHIFT_DATA 0x1c
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/* Fields in TEGRA210_PEQ_CFG */
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#define TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT 2
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#define TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK (0xf << TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT)
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#define TEGRA210_PEQ_CFG_MODE_SHIFT 0
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#define TEGRA210_PEQ_CFG_MODE_MASK (0x1 << TEGRA210_PEQ_CFG_MODE_SHIFT)
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#define TEGRA210_PEQ_RAM_CTRL_RW_READ 0
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#define TEGRA210_PEQ_RAM_CTRL_RW_WRITE (1 << 14)
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#define TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN (1 << 13)
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#define TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN (1 << 12)
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#define TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK 0x1ff
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/* PEQ register definition ends here */
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#define TEGRA210_PEQ_MAX_BIQUAD_STAGES 12
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#define TEGRA210_PEQ_MAX_CHANNELS 8
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#define TEGRA210_PEQ_BIQUAD_INIT_STAGE 5
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#define TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES * 5)
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#define TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES)
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int tegra210_peq_regmap_init(struct platform_device *pdev);
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int tegra210_peq_component_init(struct snd_soc_component *cmpnt);
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void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains,
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u32 *biquad_shifts);
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void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains,
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u32 *biquad_shifts);
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#endif
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