423 lines
10 KiB
C
423 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* An empty pmu-events.c file used when there is no architecture json files in
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* arch or when the jevents.py script cannot be run.
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*
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* The test cpu/soc is provided for testing.
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*/
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#include "pmu-events/pmu-events.h"
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#include "util/header.h"
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#include "util/pmu.h"
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#include <string.h>
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#include <stddef.h>
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static const struct pmu_event pmu_events__test_soc_cpu[] = {
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{
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.name = "l3_cache_rd",
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.event = "event=0x40",
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.desc = "L3 cache access, read",
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.topic = "cache",
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.long_desc = "Attributable Level 3 cache access, read",
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},
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{
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.name = "segment_reg_loads.any",
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.event = "event=0x6,period=200000,umask=0x80",
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.desc = "Number of segment register loads",
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.topic = "other",
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},
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{
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.name = "dispatch_blocked.any",
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.event = "event=0x9,period=200000,umask=0x20",
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.desc = "Memory cluster signals to block micro-op dispatch for any reason",
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.topic = "other",
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},
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{
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.name = "eist_trans",
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.event = "event=0x3a,period=200000,umask=0x0",
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.desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
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.topic = "other",
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},
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{
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.name = "uncore_hisi_ddrc.flux_wcmd",
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.event = "event=0x2",
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.desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
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.topic = "uncore",
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.long_desc = "DDRC write commands",
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.pmu = "hisi_sccl,ddrc",
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},
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{
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.name = "unc_cbo_xsnp_response.miss_eviction",
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.event = "event=0x22,umask=0x81",
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.desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ",
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.topic = "uncore",
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.long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
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.pmu = "uncore_cbox",
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},
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{
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.name = "event-hyphen",
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.event = "event=0xe0,umask=0x00",
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.desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ",
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.topic = "uncore",
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.long_desc = "UNC_CBO_HYPHEN",
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.pmu = "uncore_cbox",
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},
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{
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.name = "event-two-hyph",
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.event = "event=0xc0,umask=0x00",
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.desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ",
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.topic = "uncore",
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.long_desc = "UNC_CBO_TWO_HYPH",
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.pmu = "uncore_cbox",
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},
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{
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.name = "uncore_hisi_l3c.rd_hit_cpipe",
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.event = "event=0x7",
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.desc = "Total read hits. Unit: hisi_sccl,l3c ",
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.topic = "uncore",
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.long_desc = "Total read hits",
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.pmu = "hisi_sccl,l3c",
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},
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{
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.name = "uncore_imc_free_running.cache_miss",
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.event = "event=0x12",
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.desc = "Total cache misses. Unit: uncore_imc_free_running ",
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.topic = "uncore",
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.long_desc = "Total cache misses",
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.pmu = "uncore_imc_free_running",
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},
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{
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.name = "uncore_imc.cache_hits",
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.event = "event=0x34",
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.desc = "Total cache hits. Unit: uncore_imc ",
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.topic = "uncore",
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.long_desc = "Total cache hits",
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.pmu = "uncore_imc",
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},
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{
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.name = "bp_l1_btb_correct",
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.event = "event=0x8a",
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.desc = "L1 BTB Correction",
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.topic = "branch",
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},
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{
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.name = "bp_l2_btb_correct",
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.event = "event=0x8b",
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.desc = "L2 BTB Correction",
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.topic = "branch",
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},
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{
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.name = 0,
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.event = 0,
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.desc = 0,
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},
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};
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static const struct pmu_metric pmu_metrics__test_soc_cpu[] = {
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{
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.metric_expr = "1 / IPC",
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.metric_name = "CPI",
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},
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{
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.metric_expr = "inst_retired.any / cpu_clk_unhalted.thread",
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.metric_name = "IPC",
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.metric_group = "group1",
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},
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{
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.metric_expr = "idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * "
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"( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))",
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.metric_name = "Frontend_Bound_SMT",
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},
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{
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.metric_expr = "l1d\\-loads\\-misses / inst_retired.any",
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.metric_name = "dcache_miss_cpi",
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},
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{
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.metric_expr = "l1i\\-loads\\-misses / inst_retired.any",
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.metric_name = "icache_miss_cycles",
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},
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{
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.metric_expr = "(dcache_miss_cpi + icache_miss_cycles)",
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.metric_name = "cache_miss_cycles",
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.metric_group = "group1",
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},
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{
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.metric_expr = "l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit",
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.metric_name = "DCache_L2_All_Hits",
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},
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{
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.metric_expr = "max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + "
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"l2_rqsts.pf_miss + l2_rqsts.rfo_miss",
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.metric_name = "DCache_L2_All_Miss",
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},
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{
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.metric_expr = "DCache_L2_All_Hits + DCache_L2_All_Miss",
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.metric_name = "DCache_L2_All",
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},
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{
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.metric_expr = "d_ratio(DCache_L2_All_Hits, DCache_L2_All)",
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.metric_name = "DCache_L2_Hits",
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},
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{
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.metric_expr = "d_ratio(DCache_L2_All_Miss, DCache_L2_All)",
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.metric_name = "DCache_L2_Misses",
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},
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{
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.metric_expr = "ipc + M2",
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.metric_name = "M1",
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},
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{
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.metric_expr = "ipc + M1",
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.metric_name = "M2",
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},
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{
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.metric_expr = "1/M3",
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.metric_name = "M3",
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},
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{
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.metric_expr = "64 * l1d.replacement / 1000000000 / duration_time",
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.metric_name = "L1D_Cache_Fill_BW",
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},
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{
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.metric_expr = 0,
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.metric_name = 0,
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},
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};
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/* Struct used to make the PMU event table implementation opaque to callers. */
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struct pmu_events_table {
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const struct pmu_event *entries;
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};
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/* Struct used to make the PMU metric table implementation opaque to callers. */
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struct pmu_metrics_table {
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const struct pmu_metric *entries;
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};
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/*
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* Map a CPU to its table of PMU events. The CPU is identified by the
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* cpuid field, which is an arch-specific identifier for the CPU.
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* The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile
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* must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c)
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*
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* The cpuid can contain any character other than the comma.
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*/
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struct pmu_events_map {
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const char *arch;
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const char *cpuid;
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const struct pmu_events_table event_table;
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const struct pmu_metrics_table metric_table;
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};
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/*
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* Global table mapping each known CPU for the architecture to its
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* table of PMU events.
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*/
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static const struct pmu_events_map pmu_events_map[] = {
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{
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.arch = "testarch",
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.cpuid = "testcpu",
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.event_table = { pmu_events__test_soc_cpu },
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.metric_table = { pmu_metrics__test_soc_cpu },
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},
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{
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.arch = 0,
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.cpuid = 0,
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.event_table = { 0 },
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.metric_table = { 0 },
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},
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};
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static const struct pmu_event pmu_events__test_soc_sys[] = {
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{
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.name = "sys_ddr_pmu.write_cycles",
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.event = "event=0x2b",
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.desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ",
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.compat = "v8",
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.topic = "uncore",
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.pmu = "uncore_sys_ddr_pmu",
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},
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{
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.name = "sys_ccn_pmu.read_cycles",
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.event = "config=0x2c",
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.desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ",
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.compat = "0x01",
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.topic = "uncore",
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.pmu = "uncore_sys_ccn_pmu",
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},
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{
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.name = 0,
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.event = 0,
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.desc = 0,
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},
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};
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struct pmu_sys_events {
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const char *name;
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const struct pmu_events_table table;
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};
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static const struct pmu_sys_events pmu_sys_event_tables[] = {
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{
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.table = { pmu_events__test_soc_sys },
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.name = "pmu_events__test_soc_sys",
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},
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{
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.table = { 0 }
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},
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};
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int pmu_events_table_for_each_event(const struct pmu_events_table *table, pmu_event_iter_fn fn,
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void *data)
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{
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for (const struct pmu_event *pe = &table->entries[0]; pe->name; pe++) {
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int ret = fn(pe, table, data);
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if (ret)
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return ret;
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}
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return 0;
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}
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int pmu_metrics_table_for_each_metric(const struct pmu_metrics_table *table, pmu_metric_iter_fn fn,
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void *data)
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{
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for (const struct pmu_metric *pm = &table->entries[0]; pm->metric_expr; pm++) {
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int ret = fn(pm, table, data);
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if (ret)
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return ret;
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}
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return 0;
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}
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const struct pmu_events_table *perf_pmu__find_events_table(struct perf_pmu *pmu)
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{
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const struct pmu_events_table *table = NULL;
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char *cpuid = perf_pmu__getcpuid(pmu);
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int i;
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/* on some platforms which uses cpus map, cpuid can be NULL for
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* PMUs other than CORE PMUs.
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*/
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if (!cpuid)
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return NULL;
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i = 0;
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for (;;) {
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const struct pmu_events_map *map = &pmu_events_map[i++];
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if (!map->cpuid)
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break;
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if (!strcmp_cpuid_str(map->cpuid, cpuid)) {
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table = &map->event_table;
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break;
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}
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}
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free(cpuid);
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return table;
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}
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const struct pmu_metrics_table *perf_pmu__find_metrics_table(struct perf_pmu *pmu)
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{
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const struct pmu_metrics_table *table = NULL;
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char *cpuid = perf_pmu__getcpuid(pmu);
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int i;
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/* on some platforms which uses cpus map, cpuid can be NULL for
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* PMUs other than CORE PMUs.
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*/
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if (!cpuid)
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return NULL;
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i = 0;
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for (;;) {
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const struct pmu_events_map *map = &pmu_events_map[i++];
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if (!map->cpuid)
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break;
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if (!strcmp_cpuid_str(map->cpuid, cpuid)) {
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table = &map->metric_table;
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break;
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}
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}
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free(cpuid);
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return table;
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}
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const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid)
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{
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for (const struct pmu_events_map *tables = &pmu_events_map[0];
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tables->arch;
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tables++) {
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if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid))
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return &tables->event_table;
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}
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return NULL;
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}
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const struct pmu_metrics_table *find_core_metrics_table(const char *arch, const char *cpuid)
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{
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for (const struct pmu_events_map *tables = &pmu_events_map[0];
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tables->arch;
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tables++) {
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if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid))
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|
|
return &tables->metric_table;
|
||
|
|
}
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data)
|
||
|
|
{
|
||
|
|
for (const struct pmu_events_map *tables = &pmu_events_map[0]; tables->arch; tables++) {
|
||
|
|
int ret = pmu_events_table_for_each_event(&tables->event_table, fn, data);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int pmu_for_each_core_metric(pmu_metric_iter_fn fn, void *data)
|
||
|
|
{
|
||
|
|
for (const struct pmu_events_map *tables = &pmu_events_map[0];
|
||
|
|
tables->arch;
|
||
|
|
tables++) {
|
||
|
|
int ret = pmu_metrics_table_for_each_metric(&tables->metric_table, fn, data);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct pmu_events_table *find_sys_events_table(const char *name)
|
||
|
|
{
|
||
|
|
for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
|
||
|
|
tables->name;
|
||
|
|
tables++) {
|
||
|
|
if (!strcmp(tables->name, name))
|
||
|
|
return &tables->table;
|
||
|
|
}
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data)
|
||
|
|
{
|
||
|
|
for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
|
||
|
|
tables->name;
|
||
|
|
tables++) {
|
||
|
|
int ret = pmu_events_table_for_each_event(&tables->table, fn, data);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int pmu_for_each_sys_metric(pmu_metric_iter_fn fn __maybe_unused, void *data __maybe_unused)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|