87 lines
2.3 KiB
YAML
87 lines
2.3 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on APQ8084
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on APQ8084.
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See also::
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include/dt-bindings/clock/qcom,gcc-apq8084.h
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include/dt-bindings/reset/qcom,gcc-apq8084.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,gcc-apq8084
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clocks:
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items:
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- description: XO source
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- description: Sleep clock source
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- description: UFS RX symbol 0 clock
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- description: UFS RX symbol 1 clock
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- description: UFS TX symbol 0 clock
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- description: UFS TX symbol 1 clock
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- description: SATA ASIC0 clock
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- description: SATA RX clock
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- description: PCIe PIPE clock
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clock-names:
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items:
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- const: xo
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- const: sleep_clk
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- const: ufs_rx_symbol_0_clk_src
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- const: ufs_rx_symbol_1_clk_src
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- const: ufs_tx_symbol_0_clk_src
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- const: ufs_tx_symbol_1_clk_src
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- const: sata_asic0_clk
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- const: sata_rx_clk
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- const: pcie_pipe
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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/* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
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clock-controller@fc400000 {
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compatible = "qcom,gcc-apq8084";
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reg = <0xfc400000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<&ufsphy 0>,
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<&ufsphy 1>,
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<&ufsphy 2>,
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<&ufsphy 3>,
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<&sata 0>,
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<&sata 1>,
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<&pcie_phy>;
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clock-names = "xo",
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"sleep_clk",
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"ufs_rx_symbol_0_clk_src",
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"ufs_rx_symbol_1_clk_src",
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"ufs_tx_symbol_0_clk_src",
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"ufs_tx_symbol_1_clk_src",
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"sata_asic0_clk",
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"sata_rx_clk",
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"pcie_pipe";
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};
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...
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