72 lines
2.5 KiB
Plaintext
72 lines
2.5 KiB
Plaintext
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Binding for TI DaVinci Power Sleep Controller (PSC)
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The PSC provides power management, clock gating and reset functionality. It is
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primarily used for clocking.
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Required properties:
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- compatible: shall be one of:
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- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
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- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
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- reg: physical base address and size of the controller's register area
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- #clock-cells: from common clock binding; shall be set to 1
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- #power-domain-cells: from generic power domain binding; shall be set to 1.
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- clocks: phandles to clocks corresponding to the clock-names property
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- clock-names: list of parent clock names - depends on compatible value
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- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
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"pll0_sysclk4", "pll0_sysclk6", "async1"
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- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
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Optional properties:
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- #reset-cells: from reset binding; shall be set to 1 - only applicable when
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at least one local domain provides a local reset.
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Consumers:
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Clock, power domain and reset consumers shall use the local power domain
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module ID (LPSC) as the index corresponding to the clock cell. Refer to
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the device-specific datasheet to find these numbers. NB: Most local
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domains only provide a clock/power domain and not a reset.
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Examples:
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psc0: clock-controller@10000 {
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compatible = "ti,da850-psc0";
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reg = <0x10000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
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<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
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clock_names = "pll0_sysclk1", "pll0_sysclk2",
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"pll0_sysclk4", "pll0_sysclk6", "async1";
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};
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psc1: clock-controller@227000 {
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compatible = "ti,da850-psc1";
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reg = <0x227000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
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clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
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};
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/* consumer */
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dsp: dsp@11800000 {
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compatible = "ti,da850-dsp";
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reg = <0x11800000 0x40000>,
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<0x11e00000 0x8000>,
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<0x11f00000 0x8000>,
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<0x01c14044 0x4>,
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<0x01c14174 0x8>;
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reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
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interrupt-parent = <&intc>;
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interrupts = <28>;
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clocks = <&psc0 15>;
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power-domains = <&psc0 15>;
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resets = <&psc0 15>;
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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- Documentation/devicetree/bindings/power/power-domain.yaml
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- Documentation/devicetree/bindings/reset/reset.txt
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