65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal clock controller
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maintainers:
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- Michal Simek <michal.simek@xilinx.com>
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- Jolly Shah <jolly.shah@xilinx.com>
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- Rajan Vaja <rajan.vaja@xilinx.com>
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description: |
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The clock controller is a hardware block of Xilinx versal clock tree. It
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reads required input clock frequencies from the devicetree and acts as clock
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provider for all clock consumers of PS clocks.
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select: false
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properties:
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compatible:
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const: xlnx,versal-clk
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"#clock-cells":
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const: 1
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clocks:
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description: List of clock specifiers which are external input
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clocks to the given clock controller.
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items:
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- description: reference clock
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- description: alternate reference clock
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- description: alternate reference clock for programmable logic
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clock-names:
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items:
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- const: ref
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- const: alt_ref
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- const: pl_alt_ref
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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versal_clk: clock-controller {
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#clock-cells = <1>;
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compatible = "xlnx,versal-clk";
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clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
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clock-names = "ref", "alt_ref", "pl_alt_ref";
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};
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};
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};
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...
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