76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DSI 7nm PHY
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maintainers:
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- Jonathan Marek <jonathan@marek.ca>
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allOf:
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- $ref: dsi-phy-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,dsi-phy-7nm
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- qcom,dsi-phy-7nm-8150
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- qcom,sc7280-dsi-phy-7nm
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- qcom,sm6375-dsi-phy-7nm
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- qcom,sm8350-dsi-phy-5nm
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- qcom,sm8450-dsi-phy-5nm
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- qcom,sm8550-dsi-phy-4nm
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reg:
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items:
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- description: dsi phy register set
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- description: dsi phy lane register set
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- description: dsi pll register set
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reg-names:
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items:
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- const: dsi_phy
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- const: dsi_phy_lane
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- const: dsi_pll
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vdds-supply:
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description: |
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Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
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phy-type:
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description: D-PHY (default) or C-PHY mode
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enum: [ 10, 11 ]
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default: 10
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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dsi-phy@ae94400 {
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compatible = "qcom,dsi-phy-7nm";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94900 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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vdds-supply = <&vreg_l5a_0p88>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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};
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