100 lines
2.3 KiB
YAML
100 lines
2.3 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8250 Display DPU
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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const: qcom,sm8250-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display ahb clock
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- description: Display hf axi clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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- const: vsync
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sm8250.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sm8250-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "iface", "bus", "core", "vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8250_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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};
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...
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