64 lines
1.3 KiB
YAML
64 lines
1.3 KiB
YAML
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Altera mSGDMA IP core
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Olivier Dautricourt <olivierdautricourt@gmail.com>
|
||
|
|
|
||
|
|
description: |
|
||
|
|
Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
|
||
|
|
intellectual property (IP)
|
||
|
|
|
||
|
|
allOf:
|
||
|
|
- $ref: dma-controller.yaml#
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
const: altr,socfpga-msgdma
|
||
|
|
|
||
|
|
reg:
|
||
|
|
items:
|
||
|
|
- description: Control and Status Register Slave Port
|
||
|
|
- description: Descriptor Slave Port
|
||
|
|
- description: Response Slave Port (Optional)
|
||
|
|
minItems: 2
|
||
|
|
|
||
|
|
reg-names:
|
||
|
|
items:
|
||
|
|
- const: csr
|
||
|
|
- const: desc
|
||
|
|
- const: resp
|
||
|
|
minItems: 2
|
||
|
|
|
||
|
|
interrupts:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
"#dma-cells":
|
||
|
|
const: 1
|
||
|
|
description:
|
||
|
|
The cell identifies the channel id (must be 0)
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- reg-names
|
||
|
|
- interrupts
|
||
|
|
|
||
|
|
unevaluatedProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||
|
|
|
||
|
|
msgdma_controller: dma-controller@ff200b00 {
|
||
|
|
compatible = "altr,socfpga-msgdma";
|
||
|
|
reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
|
||
|
|
reg-names = "csr", "desc", "resp";
|
||
|
|
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#dma-cells = <1>;
|
||
|
|
};
|