64 lines
1.6 KiB
YAML
64 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 L2-cache Control Block
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description: |
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By means of the System Controller Baikal-T1 SoC exposes a few settings to
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tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
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to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
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L2-cache controller block is responsible for the tuning. Its DT node is
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supposed to be a child of the system controller.
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properties:
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compatible:
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const: baikal,bt1-l2-ctl
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reg:
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maxItems: 1
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baikal,l2-ws-latency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Cycles of latency for Way-select RAM accesses
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default: 0
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minimum: 0
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maximum: 3
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baikal,l2-tag-latency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Cycles of latency for Tag RAM accesses
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default: 0
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minimum: 0
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maximum: 3
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baikal,l2-data-latency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Cycles of latency for Data RAM accesses
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default: 1
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minimum: 0
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maximum: 3
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additionalProperties: false
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required:
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- compatible
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examples:
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- |
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l2@1f04d028 {
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compatible = "baikal,bt1-l2-ctl";
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reg = <0x1f04d028 0x004>;
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baikal,l2-ws-latency = <1>;
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baikal,l2-tag-latency = <1>;
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baikal,l2-data-latency = <2>;
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};
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...
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