59 lines
3.0 KiB
Plaintext
59 lines
3.0 KiB
Plaintext
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* Xilinx SDFEC(16nm) IP *
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The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
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which provides high-throughput LDPC and Turbo Code implementations.
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The LDPC decode & encode functionality is capable of covering a range of
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customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
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principally covers codes used by LTE. The FEC Engine offers significant
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power and area savings versus implementations done in the FPGA fabric.
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Required properties:
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- compatible: Must be "xlnx,sd-fec-1.1"
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- clock-names : List of input clock names from the following:
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- "core_clk", Main processing clock for processing core (required)
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- "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
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- "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
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- "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
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- "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
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- "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
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- "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
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- "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
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- clocks : Clock phandles (see clock_bindings.txt for details).
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- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
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location and length.
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- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
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being used.
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- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
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driven with a fixed value and is not present on the device, a value of 1
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configures the DIN_WORDS to be block based, while a value of 2 configures the
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DIN_WORDS input to be supplied for each AXI transaction.
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- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
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configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
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of "4x128b".
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- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
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driven with a fixed value and is not present on the device, a value of 1
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configures the DOUT_WORDS to be block based, while a value of 2 configures the
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DOUT_WORDS input to be supplied for each AXI transaction.
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- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
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configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
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of "4x128b".
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Optional properties:
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- interrupts: should contain SDFEC interrupt number
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Example
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---------------------------------------
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sd_fec_0: sd-fec@a0040000 {
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compatible = "xlnx,sd-fec-1.1";
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clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
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clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
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reg = <0x0 0xa0040000 0x0 0x40000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <1 0>;
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xlnx,sdfec-code = "ldpc";
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xlnx,sdfec-din-words = <0>;
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xlnx,sdfec-din-width = <2>;
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xlnx,sdfec-dout-words = <0>;
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xlnx,sdfec-dout-width = <1>;
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};
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