111 lines
2.6 KiB
YAML
111 lines
2.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: TI J721E PCI EP (PCIe Wrapper)
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: "cdns-pcie-ep.yaml#"
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-ep
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- description: PCIe EP controller in AM64
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items:
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- const: ti,am64-pcie-ep
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- const: ti,j721e-pcie-ep
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- description: PCIe EP controller in J7200
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items:
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- const: ti,j7200-pcie-ep
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- const: ti,j721e-pcie-ep
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: intd_cfg
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- const: user_cfg
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- const: reg
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- const: mem
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ti,syscon-pcie-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the SYSCON entry
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- description: pcie_ctrl register offset within SYSCON
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description: Specifier for configuring PCIe mode and link speed.
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 1
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description: clock-specifier to represent input to the PCIe
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clock-names:
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items:
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- const: fck
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dma-coherent:
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description: Indicates that the PCIe IP block can ensure the coherency
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: link_state
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required:
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- compatible
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- reg
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- reg-names
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- ti,syscon-pcie-ctrl
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- max-link-speed
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- num-lanes
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- power-domains
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- clocks
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- clock-names
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- max-functions
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- phys
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- phy-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie0_ep: pcie-ep@d000000 {
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compatible = "ti,j721e-pcie-ep";
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reg = <0x00 0x02900000 0x00 0x1000>,
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<0x00 0x02907000 0x00 0x400>,
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<0x00 0x0d000000 0x00 0x00800000>,
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<0x00 0x10000000 0x00 0x08000000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "mem";
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ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
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max-link-speed = <3>;
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num-lanes = <2>;
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power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 239 1>;
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clock-names = "fck";
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max-functions = /bits/ 8 <6>;
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dma-coherent;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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};
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};
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