154 lines
4.9 KiB
YAML
154 lines
4.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM8909 TLMM block
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maintainers:
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- Stephan Gerhold <stephan@gerhold.net>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,msm8909-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-msm8909-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-msm8909-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-msm8909-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
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sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
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qdsd_data2, qdsd_data3 ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
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atest_char1, atest_char2, atest_char3, atest_combodac,
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atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
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bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
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blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
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blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
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blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
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blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
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blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
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cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
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dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
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ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
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gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
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gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
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nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
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pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
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pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
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pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
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prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
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pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
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pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
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qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
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qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
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qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
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qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
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smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
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uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
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uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
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wcss_bt, wcss_fm, wcss_wlan ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@1000000 {
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compatible = "qcom,msm8909-tlmm";
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reg = <0x1000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 113>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-wo-subnode-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-subnodes-state {
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rx-pins {
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pins = "gpio4";
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function = "blsp_uart1";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio5";
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function = "blsp_uart1";
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bias-disable;
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};
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};
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};
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...
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