57 lines
2.0 KiB
Plaintext
57 lines
2.0 KiB
Plaintext
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Every GPIO controller node must have #gpio-cells property defined,
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this information will be used to translate gpio-specifiers.
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On CPM1 devices, all ports are using slightly different register layouts.
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Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
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On CPM2 devices, all ports are 32bit ports and use a common register layout.
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Required properties:
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- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
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"fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
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"fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- gpio-controller : Marks the port as GPIO controller.
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Optional properties:
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- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
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on CPM1), this item tells which ports have an associated interrupt (ports are
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listed in the same order as in PCINT register)
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- interrupts : This property provides the list of interrupt for each GPIO having
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one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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many interrupts as number of ones in the mask property. The first interrupt in
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the list corresponds to the most significant bit of the mask.
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Example of four SOC GPIO banks defined as gpio-controller nodes:
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CPM1_PIO_A: gpio-controller@950 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-a";
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reg = <0x950 0x10>;
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gpio-controller;
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};
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CPM1_PIO_B: gpio-controller@ab8 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-b";
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reg = <0xab8 0x10>;
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gpio-controller;
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};
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CPM1_PIO_C: gpio-controller@960 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-c";
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reg = <0x960 0x10>;
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fsl,cpm1-gpio-irq-mask = <0x0fff>;
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interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
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interrupt-parent = <&CPM_PIC>;
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gpio-controller;
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};
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CPM1_PIO_E: gpio-controller@ac8 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-e";
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reg = <0xac8 0x18>;
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gpio-controller;
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};
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