402 lines
11 KiB
YAML
402 lines
11 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare USB3 Controller
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maintainers:
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- Felipe Balbi <balbi@kernel.org>
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description:
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This is usually a subnode to DWC3 glue to which it is connected, but can also
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be presented as a standalone DT node with an optional vendor-specific
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compatible string.
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allOf:
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- $ref: usb-drd.yaml#
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- if:
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properties:
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dr_mode:
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const: peripheral
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required:
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- dr_mode
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then:
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$ref: usb.yaml#
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else:
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$ref: usb-xhci.yaml#
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properties:
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compatible:
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contains:
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oneOf:
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- const: snps,dwc3
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- const: synopsys,dwc3
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deprecated: true
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reg:
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maxItems: 1
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interrupts:
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description:
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It's either a single common DWC3 interrupt (dwc_usb3) or individual
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interrupts for the host, gadget and DRD modes.
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minItems: 1
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maxItems: 3
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interrupt-names:
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minItems: 1
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maxItems: 3
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oneOf:
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- const: dwc_usb3
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- items:
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enum: [host, peripheral, otg]
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clocks:
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description:
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In general the core supports three types of clocks. bus_early is a
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SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
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PHY is suspended. suspend clocks a small part of the USB3 core when
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SS PHY in P3. But particular cases may differ from that having less
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or more clock sources with another names.
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clock-names:
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contains:
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anyOf:
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- enum: [bus_early, ref, suspend]
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- true
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dma-coherent: true
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iommus:
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maxItems: 1
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usb-phy:
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minItems: 1
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items:
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- description: USB2/HS PHY
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- description: USB3/SS PHY
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phys:
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- usb2-phy
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- usb3-phy
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power-domains:
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description:
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The DWC3 has 2 power-domains. The power management unit (PMU) and
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everything else. The PMU is typically always powered and may not have an
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entry.
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minItems: 1
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items:
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- description: Core
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- description: Power management unit
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resets:
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minItems: 1
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snps,usb2-lpm-disable:
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description: Indicate if we don't want to enable USB2 HW LPM for host
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mode.
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type: boolean
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snps,usb3_lpm_capable:
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description: Determines if platform is USB3 LPM capable
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type: boolean
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snps,usb2-gadget-lpm-disable:
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description: Indicate if we don't want to enable USB2 HW LPM for gadget
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mode.
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type: boolean
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snps,dis-start-transfer-quirk:
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description:
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When set, disable isoc START TRANSFER command failure SW work-around
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for DWC_usb31 version 1.70a-ea06 and prior.
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type: boolean
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snps,disable_scramble_quirk:
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description:
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True when SW should disable data scrambling. Only really useful for FPGA
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builds.
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type: boolean
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snps,has-lpm-erratum:
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description: True when DWC3 was configured with LPM Erratum enabled
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type: boolean
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snps,lpm-nyet-threshold:
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description: LPM NYET threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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snps,u2exit_lfps_quirk:
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description: Set if we want to enable u2exit lfps quirk
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type: boolean
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snps,u2ss_inp3_quirk:
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description: Set if we enable P3 OK for U2/SS Inactive quirk
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type: boolean
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snps,req_p1p2p3_quirk:
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description:
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When set, the core will always request for P1/P2/P3 transition sequence.
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type: boolean
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snps,del_p1p2p3_quirk:
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description:
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When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
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occur.
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type: boolean
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snps,del_phy_power_chg_quirk:
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description: When set core will delay PHY power change from P0 to P1/P2/P3.
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type: boolean
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snps,lfps_filter_quirk:
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description: When set core will filter LFPS reception.
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type: boolean
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snps,rx_detect_poll_quirk:
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description:
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when set core will disable a 400us delay to start Polling LFPS after
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RX.Detect.
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type: boolean
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snps,tx_de_emphasis_quirk:
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description: When set core will set Tx de-emphasis value
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type: boolean
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snps,tx_de_emphasis:
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description:
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The value driven to the PHY is controlled by the LTSSM during USB3
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Compliance mode.
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$ref: /schemas/types.yaml#/definitions/uint8
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enum:
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- 0 # -6dB de-emphasis
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- 1 # -3.5dB de-emphasis
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- 2 # No de-emphasis
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snps,dis_u3_susphy_quirk:
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description: When set core will disable USB3 suspend phy
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type: boolean
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snps,dis_u2_susphy_quirk:
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description: When set core will disable USB2 suspend phy
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type: boolean
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snps,dis_enblslpm_quirk:
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description:
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When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
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to the PHY.
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type: boolean
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snps,dis-u1-entry-quirk:
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description: Set if link entering into U1 needs to be disabled
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type: boolean
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snps,dis-u2-entry-quirk:
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description: Set if link entering into U2 needs to be disabled
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type: boolean
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snps,dis_rxdet_inp3_quirk:
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description:
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When set core will disable receiver detection in PHY P3 power state.
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type: boolean
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snps,dis-u2-freeclk-exists-quirk:
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description:
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When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
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PHY doesn't provide a free-running PHY clock.
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type: boolean
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snps,dis-del-phy-power-chg-quirk:
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description:
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When set core will change PHY power from P0 to P1/P2/P3 without delay.
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type: boolean
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snps,dis-tx-ipgap-linecheck-quirk:
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description: When set, disable u2mac linestate check during HS transmit
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type: boolean
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snps,parkmode-disable-ss-quirk:
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description:
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When set, all SuperSpeed bus instances in park mode are disabled.
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type: boolean
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snps,dis_metastability_quirk:
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description:
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When set, disable metastability workaround. CAUTION! Use only if you are
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absolutely sure of it.
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type: boolean
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snps,dis-split-quirk:
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description:
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When set, change the way URBs are handled by the driver. Needed to
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avoid -EPROTO errors with usbhid on some devices (Hikey 970).
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type: boolean
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snps,gfladj-refclk-lpm-sel-quirk:
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description:
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When set, run the SOF/ITP counter based on ref_clk.
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type: boolean
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snps,resume-hs-terminations:
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description:
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Fix the issue of HS terminations CRC error on resume by enabling this
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quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
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of resume. This option is to support certain legacy ULPI PHYs.
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type: boolean
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snps,is-utmi-l1-suspend:
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description:
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True when DWC3 asserts output signal utmi_l1_suspend_n, false when
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asserts utmi_sleep_n.
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type: boolean
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snps,hird-threshold:
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description: HIRD threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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snps,hsphy_interface:
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description:
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High-Speed PHY interface selection between UTMI+ and ULPI when the
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DWC_USB3_HSPHY_INTERFACE has value 3.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [utmi, ulpi]
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snps,quirk-frame-length-adjustment:
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description:
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Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
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length adjustment when the fladj_30mhz_sdbnd signal is invalid or
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incorrect.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x3f
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snps,ref-clock-period-ns:
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description:
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Value for REFCLKPER field of GUCTL register for reference clock period in
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nanoseconds, when the hardware set default does not match the actual
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clock.
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This binding is deprecated. Instead, provide an appropriate reference clock.
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minimum: 8
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maximum: 62
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deprecated: true
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snps,rx-thr-num-pkt-prd:
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description:
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Periodic ESS RX packet threshold count (host mode only). Set this and
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snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,rx-max-burst-prd:
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description:
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Max periodic ESS RX burst size (host mode only). Set this and
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snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,tx-thr-num-pkt-prd:
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description:
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Periodic ESS TX packet threshold count (host mode only). Set this and
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snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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snps,tx-max-burst-prd:
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description:
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Max periodic ESS TX burst size (host mode only). Set this and
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snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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tx-fifo-resize:
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description: Determines if the TX fifos can be dynamically resized depending
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on the number of IN endpoints used and if bursting is supported. This
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may help improve bandwidth on platforms with higher system latencies, as
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increased fifo space allows for the controller to prefetch data into its
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internal memory.
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type: boolean
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tx-fifo-max-num:
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description: Specifies the max number of packets the txfifo resizing logic
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can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
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higher the number, the more fifo space the txfifo resizing logic will
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allocate for that endpoint.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 3
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snps,incr-burst-type-adjustment:
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description:
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Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
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burst type enable and INCRx type. A single value means INCRX burst mode
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enabled. If more than one value specified, undefined length INCR burst
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type will be enabled with burst lengths utilized up to the maximum
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of the values passed in this property.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 8
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uniqueItems: true
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items:
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enum: [1, 4, 8, 16, 32, 64, 128, 256]
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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This port is used with the 'usb-role-switch' property to connect the
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dwc3 to type C connector.
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wakeup-source:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Enable USB remote wakeup.
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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examples:
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- |
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usb@4a030000 {
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compatible = "snps,dwc3";
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reg = <0x4a030000 0xcfff>;
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interrupts = <0 92 4>;
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usb-phy = <&usb2_phy>, <&usb3_phy>;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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||
|
|
};
|
||
|
|
- |
|
||
|
|
usb@4a000000 {
|
||
|
|
compatible = "snps,dwc3";
|
||
|
|
reg = <0x4a000000 0xcfff>;
|
||
|
|
interrupts = <0 92 4>;
|
||
|
|
clocks = <&clk 1>, <&clk 2>, <&clk 3>;
|
||
|
|
clock-names = "bus_early", "ref", "suspend";
|
||
|
|
phys = <&usb2_phy>, <&usb3_phy>;
|
||
|
|
phy-names = "usb2-phy", "usb3-phy";
|
||
|
|
snps,dis_u2_susphy_quirk;
|
||
|
|
snps,dis_enblslpm_quirk;
|
||
|
|
};
|
||
|
|
...
|