305 lines
8.6 KiB
C
305 lines
8.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
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* Stack switching code can no longer reliably rely on the fact that
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* if we are NOT in user mode, stack is switched to kernel mode.
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* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
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* it's prologue including stack switching from user mode
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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* we also need to explicitly do this. The problem in macros
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* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
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* was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
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*
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* Vineetg: May 5th 2008
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* -Modified CALLEE_REG save/restore macros to handle the fact that
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* r25 contains the kernel current task ptr
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* - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
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* - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
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* address Write back load ld.ab instead of separate ld/add instn
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*
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* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
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*/
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#ifndef __ASM_ARC_ENTRY_COMPACT_H
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#define __ASM_ARC_ENTRY_COMPACT_H
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#include <asm/asm-offsets.h>
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#include <asm/irqflags-compact.h>
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#include <asm/thread_info.h> /* For THREAD_SIZE */
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/*--------------------------------------------------------------
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* Switch to Kernel Mode stack if SP points to User Mode stack
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*
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* Entry : r9 contains pre-IRQ/exception/trap status32
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* Exit : SP set to K mode stack
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* SP at the time of entry (K/U) saved @ pt_regs->sp
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* Clobbers: r9
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*-------------------------------------------------------------*/
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.macro SWITCH_TO_KERNEL_STK
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/* User Mode when this happened ? Yes: Proceed to switch stack */
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bbit1 r9, STATUS_U_BIT, 88f
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/* OK we were already in kernel mode when this event happened, thus can
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* assume SP is kernel mode SP. _NO_ need to do any stack switching
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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/* However....
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* If Level 2 Interrupts enabled, we may end up with a corner case:
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* 1. User Task executing
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* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
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* 3. But before it could switch SP from USER to KERNEL stack
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* a L2 IRQ "Interrupts" L1
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* Thay way although L2 IRQ happened in Kernel mode, stack is still
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* not switched.
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* To handle this, we may need to switch stack even if in kernel mode
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* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
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*/
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brlo sp, VMALLOC_START, 88f
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/* TODO: vineetg:
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* We need to be a bit more cautious here. What if a kernel bug in
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* L1 ISR, caused SP to go whaco (some small value which looks like
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* USER stk) and then we take L2 ISR.
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* Above brlo alone would treat it as a valid L1-L2 scenario
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* instead of shouting around
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* The only feasible way is to make sure this L2 happened in
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* L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
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* L1 ISR before it switches stack
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*/
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#endif
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/*------Intr/Ecxp happened in kernel mode, SP already setup ------ */
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/* save it nevertheless @ pt_regs->sp for uniformity */
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b.d 66f
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st sp, [sp, PT_sp - SZ_PT_REGS]
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88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
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GET_CURR_TASK_ON_CPU r9
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/* With current tsk in r9, get it's kernel mode stack base */
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GET_TSK_STACK_BASE r9, r9
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/* save U mode SP @ pt_regs->sp */
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st sp, [r9, PT_sp - SZ_PT_REGS]
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/* final SP switch */
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mov sp, r9
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66:
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.endm
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/*------------------------------------------------------------
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* "FAKE" a rtie to return from CPU Exception context
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* This is to re-enable Exceptions within exception
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* Look at EV_ProtV to see how this is actually used
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*-------------------------------------------------------------*/
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.macro FAKE_RET_FROM_EXCPN
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lr r9, [status32]
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bclr r9, r9, STATUS_AE_BIT
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or r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK)
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sr r9, [erstatus]
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mov r9, 55f
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sr r9, [eret]
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rtie
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55:
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.endm
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/*--------------------------------------------------------------
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* For early Exception/ISR Prologue, a core reg is temporarily needed to
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* code the rest of prolog (stack switching). This is done by stashing
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* it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
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*
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* Before saving the full regfile - this reg is restored back, only
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* to be saved again on kernel mode stack, as part of pt_regs.
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*-------------------------------------------------------------*/
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.macro PROLOG_FREEUP_REG reg, mem
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st \reg, [\mem]
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.endm
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.macro PROLOG_RESTORE_REG reg, mem
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ld \reg, [\mem]
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.endm
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/*--------------------------------------------------------------
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* Exception Entry prologue
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* -Switches stack to K mode (if not already)
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* -Saves the register file
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*
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* After this it is safe to call the "C" handlers
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*-------------------------------------------------------------*/
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.macro EXCEPTION_PROLOGUE
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/* Need at least 1 reg to code the early exception prologue */
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PROLOG_FREEUP_REG r9, @ex_saved_reg1
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/* U/K mode at time of exception (stack not switched if already K) */
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lr r9, [erstatus]
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/* ARC700 doesn't provide auto-stack switching */
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SWITCH_TO_KERNEL_STK
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#ifdef CONFIG_ARC_CURR_IN_REG
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/* Treat r25 as scratch reg (save on stack) and load with "current" */
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PUSH r25
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GET_CURR_TASK_ON_CPU r25
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#else
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sub sp, sp, 4
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#endif
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st.a r0, [sp, -8] /* orig_r0 needed for syscall (skip ECR slot) */
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sub sp, sp, 4 /* skip pt_regs->sp, already saved above */
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/* Restore r9 used to code the early prologue */
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PROLOG_RESTORE_REG r9, @ex_saved_reg1
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/* now we are ready to save the regfile */
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SAVE_R0_TO_R12
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PUSH gp
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PUSH fp
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PUSH blink
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PUSHAX eret
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PUSHAX erstatus
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PUSH lp_count
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PUSHAX lp_end
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PUSHAX lp_start
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PUSHAX erbta
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lr r10, [ecr]
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st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by system call or Exceptions
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* SP should always be pointing to the next free stack element
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* when entering this macro.
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*
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro EXCEPTION_EPILOGUE
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POPAX erbta
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POPAX lp_start
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POPAX lp_end
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POP r9
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mov lp_count, r9 ;LD to lp_count is not allowed
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POPAX erstatus
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POPAX eret
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POP blink
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POP fp
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POP gp
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RESTORE_R12_TO_R0
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#ifdef CONFIG_ARC_CURR_IN_REG
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ld r25, [sp, 12]
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#endif
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ld sp, [sp] /* restore original sp */
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/* orig_r0, ECR, user_r25 skipped automatically */
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.endm
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/* Dummy ECR values for Interrupts */
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#define event_IRQ1 0x0031abcd
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#define event_IRQ2 0x0032abcd
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.macro INTERRUPT_PROLOGUE LVL
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/* free up r9 as scratchpad */
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PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
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/* Which mode (user/kernel) was the system in when intr occurred */
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lr r9, [status32_l\LVL\()]
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SWITCH_TO_KERNEL_STK
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#ifdef CONFIG_ARC_CURR_IN_REG
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/* Treat r25 as scratch reg (save on stack) and load with "current" */
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PUSH r25
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GET_CURR_TASK_ON_CPU r25
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#else
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sub sp, sp, 4
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#endif
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PUSH 0x003\LVL\()abcd /* Dummy ECR */
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sub sp, sp, 8 /* skip orig_r0 (not needed)
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skip pt_regs->sp, already saved above */
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/* Restore r9 used to code the early prologue */
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PROLOG_RESTORE_REG r9, @int\LVL\()_saved_reg
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SAVE_R0_TO_R12
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PUSH gp
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PUSH fp
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PUSH blink
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PUSH ilink\LVL\()
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PUSHAX status32_l\LVL\()
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PUSH lp_count
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PUSHAX lp_end
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PUSHAX lp_start
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PUSHAX bta_l\LVL\()
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by interrupt handlers.
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*
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro INTERRUPT_EPILOGUE LVL
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POPAX bta_l\LVL\()
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POPAX lp_start
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POPAX lp_end
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POP r9
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mov lp_count, r9 ;LD to lp_count is not allowed
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POPAX status32_l\LVL\()
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POP ilink\LVL\()
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POP blink
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POP fp
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POP gp
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RESTORE_R12_TO_R0
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#ifdef CONFIG_ARC_CURR_IN_REG
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ld r25, [sp, 12]
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#endif
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ld sp, [sp] /* restore original sp */
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/* orig_r0, ECR, user_r25 skipped automatically */
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.endm
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/* Get thread_info of "current" tsk */
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.macro GET_CURR_THR_INFO_FROM_SP reg
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bic \reg, sp, (THREAD_SIZE - 1)
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.endm
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/* Get CPU-ID of this core */
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.macro GET_CPU_ID reg
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lr \reg, [identity]
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lsr \reg, \reg, 8
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bmsk \reg, \reg, 7
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.endm
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#endif /* __ASM_ARC_ENTRY_COMPACT_H */
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