107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#include <linux/dma-map-ops.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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/*
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* ARCH specific callbacks for generic noncoherent DMA ops
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* - hardware IOC not available (or "dma-coherent" not set for device in DT)
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* - But still handle both coherent and non-coherent requests from caller
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*
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* For DMA coherent hardware (IOC) generic code suffices
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*/
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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/*
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* Evict any existing L1 and/or L2 lines for the backing page
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* in case it was used earlier as a normal "cached" page.
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* Yeah this bit us - STAR 9000898266
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*
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* Although core does call flush_cache_vmap(), it gets kvaddr hence
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* can't be used to efficiently flush L1 and/or L2 which need paddr
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* Currently flush_cache_vmap nukes the L1 cache completely which
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* will be optimized as a separate commit
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*/
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dma_cache_wback_inv(page_to_phys(page), size);
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}
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/*
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* Cache operations depending on function and direction argument, inspired by
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* https://lore.kernel.org/lkml/20180518175004.GF17671@n2100.armlinux.org.uk
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* "dma_sync_*_for_cpu and direction=TO_DEVICE (was Re: [PATCH 02/20]
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* dma-mapping: provide a generic dma-noncoherent implementation)"
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*
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* | map == for_device | unmap == for_cpu
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* |----------------------------------------------------------------
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* TO_DEV | writeback writeback | none none
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* FROM_DEV | invalidate invalidate | invalidate* invalidate*
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* BIDIR | writeback+inv writeback+inv | invalidate invalidate
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*
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* [*] needed for CPU speculative prefetches
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*
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* NOTE: we don't check the validity of direction argument as it is done in
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* upper layer functions (in include/linux/dma-mapping.h)
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*/
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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dma_cache_wback(paddr, size);
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break;
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case DMA_FROM_DEVICE:
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dma_cache_inv(paddr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv(paddr, size);
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break;
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default:
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break;
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}
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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break;
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/* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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dma_cache_inv(paddr, size);
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break;
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default:
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break;
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}
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}
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/*
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* Plug in direct dma map ops.
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*/
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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/*
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* IOC hardware snoops all DMA traffic keeping the caches consistent
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* with memory - eliding need for any explicit cache maintenance of
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* DMA buffers.
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*/
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if (is_isa_arcv2() && ioc_enable && coherent)
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dev->dma_coherent = true;
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dev_info(dev, "use %scoherent DMA ops\n",
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dev->dma_coherent ? "" : "non");
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}
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