519 lines
7.3 KiB
Plaintext
519 lines
7.3 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "aspeed-g4.dtsi"
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#include <dt-bindings/gpio/aspeed-gpio.h>
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/ {
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model = "Quanta Q71L BMC";
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compatible = "quanta,q71l-bmc", "aspeed,ast2400";
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aliases {
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i2c14 = &i2c_pcie2;
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i2c15 = &i2c_pcie3;
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i2c16 = &i2c_pcie6;
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i2c17 = &i2c_pcie7;
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i2c18 = &i2c_pcie1;
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i2c19 = &i2c_pcie4;
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i2c20 = &i2c_pcie5;
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i2c21 = &i2c_pcie8;
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i2c22 = &i2c_pcie9;
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i2c23 = &i2c_pcie10;
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i2c24 = &i2c_ssd1;
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i2c25 = &i2c_ssd2;
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i2c26 = &i2c_psu4;
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i2c27 = &i2c_psu1;
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i2c28 = &i2c_psu3;
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i2c29 = &i2c_psu2;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200 earlycon";
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};
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memory@40000000 {
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reg = <0x40000000 0x8000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vga_memory: framebuffer@47800000 {
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no-map;
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reg = <0x47800000 0x00800000>; /* 8MB */
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat {
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gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
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};
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power {
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gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
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};
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identify {
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gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
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};
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
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<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
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<&adc 8>, <&adc 9>, <&adc 10>;
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};
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iio-hwmon-battery {
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compatible = "iio-hwmon";
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io-channels = <&adc 11>;
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};
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i2c1mux: i2cmux {
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compatible = "i2c-mux-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
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i2c-parent = <&i2c1>;
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};
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};
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&fmc {
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status = "okay";
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flash@0 {
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status = "okay";
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label = "bmc";
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m25p,fast-read;
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#include "openbmc-flash-layout.dtsi"
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};
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};
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&spi {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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flash@0 {
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status = "okay";
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m25p,fast-read;
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label = "pnor";
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};
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
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&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
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};
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&p2a {
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status = "okay";
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memory-region = <&vga_memory>;
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};
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&ibt {
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status = "okay";
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};
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&lpc_ctrl {
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status = "okay";
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};
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&lpc_snoop {
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status = "okay";
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snoop-ports = <0x80>;
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};
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&mac0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii1_default>;
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use-ncsi;
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};
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&mac1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
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};
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&uart1 {
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status = "okay";
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};
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&uart5 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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/* temp2 inlet */
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tmp75@4c {
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compatible = "ti,tmp75";
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reg = <0x4c>;
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};
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/* temp3 */
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tmp75@4e {
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compatible = "ti,tmp75";
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reg = <0x4e>;
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};
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/* temp1 */
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tmp75@4f {
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compatible = "ti,tmp75";
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reg = <0x4f>;
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};
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/* Baseboard FRU */
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eeprom@54 {
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compatible = "atmel,24c64";
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reg = <0x54>;
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};
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/* FP FRU */
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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&i2c2 {
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status = "okay";
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/* 0: PCIe Slot 2,
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* Slot 3,
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* Slot 6,
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* Slot 7
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*/
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i2c-switch@74 {
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compatible = "nxp,pca9546";
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reg = <0x74>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect; /* may use mux@77 next. */
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i2c_pcie2: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c_pcie3: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c_pcie6: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c_pcie7: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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/* 0: PCIe Slot 1,
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* Slot 4,
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* Slot 5,
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* Slot 8,
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* Slot 9,
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* Slot 10,
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* SSD 1,
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* SSD 2
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*/
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i2c-switch@77 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x77>;
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i2c-mux-idle-disconnect; /* may use mux@74 next. */
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i2c_pcie1: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c_pcie4: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c_pcie5: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c_pcie8: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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i2c_pcie9: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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i2c_pcie10: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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i2c_ssd1: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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i2c_ssd2: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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};
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};
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&i2c3 {
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status = "okay";
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/* BIOS FRU */
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eeprom@56 {
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compatible = "atmel,24c64";
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reg = <0x56>;
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};
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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/* 0: PSU4
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* PSU1
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* PSU3
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* PSU2
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*/
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i2c-switch@70 {
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compatible = "nxp,pca9546";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c_psu4: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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psu@59 {
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compatible = "pmbus";
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reg = <0x59>;
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};
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};
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i2c_psu1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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psu@58 {
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compatible = "pmbus";
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reg = <0x58>;
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};
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};
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i2c_psu3: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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psu@58 {
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compatible = "pmbus";
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reg = <0x58>;
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};
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};
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i2c_psu2: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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psu@59 {
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compatible = "pmbus";
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reg = <0x59>;
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};
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};
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};
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/* PDB FRU */
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eeprom@52 {
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compatible = "atmel,24c64";
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reg = <0x52>;
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};
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};
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&i2c8 {
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status = "okay";
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/* BMC FRU */
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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};
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};
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&vuart {
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status = "okay";
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};
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&wdt2 {
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status = "okay";
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};
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&adc {
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status = "okay";
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};
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&pwm_tacho {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0_default
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&pinctrl_pwm1_default
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&pinctrl_pwm2_default
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&pinctrl_pwm3_default>;
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fan@0 {
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reg = <0x00>;
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|
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aspeed,fan-tach-ch = /bits/ 8 <0x00>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@1 {
|
||
|
|
reg = <0x01>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@2 {
|
||
|
|
reg = <0x02>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@3 {
|
||
|
|
reg = <0x03>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@4 {
|
||
|
|
reg = <0x00>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@5 {
|
||
|
|
reg = <0x01>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@6 {
|
||
|
|
reg = <0x02>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fan@7 {
|
||
|
|
reg = <0x03>;
|
||
|
|
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c1mux {
|
||
|
|
i2c@0 {
|
||
|
|
reg = <0>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
/* Memory Riser 1 FRU */
|
||
|
|
eeprom@50 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x50>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 2 FRU */
|
||
|
|
eeprom@51 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x51>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 3 FRU */
|
||
|
|
eeprom@52 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x52>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 4 FRU */
|
||
|
|
eeprom@53 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x53>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c@1 {
|
||
|
|
reg = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
/* Memory Riser 5 FRU */
|
||
|
|
eeprom@50 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x50>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 6 FRU */
|
||
|
|
eeprom@51 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x51>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 7 FRU */
|
||
|
|
eeprom@52 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x52>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Memory Riser 8 FRU */
|
||
|
|
eeprom@53 {
|
||
|
|
compatible = "atmel,24c02";
|
||
|
|
reg = <0x53>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|