532 lines
12 KiB
Plaintext
532 lines
12 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's Exynos4210 SoC device tree source
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2010-2011 Linaro Ltd.
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* www.linaro.org
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*
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* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
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* based board files can include this file and provide values for board specific
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
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* nodes can be added to this file.
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*/
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#include "exynos4.dtsi"
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#include "exynos4-cpu-thermal.dtsi"
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/ {
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compatible = "samsung,exynos4210", "samsung,exynos4";
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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};
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bus_acp: bus-acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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bus_acp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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};
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bus_display: bus-display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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status = "disabled";
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bus_display_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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};
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};
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bus_dmc: bus-dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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bus_dmc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <1025000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <1050000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1150000>;
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opp-suspend;
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};
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};
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};
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bus_fsys: bus-fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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bus_fsys_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-10000000 {
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opp-hz = /bits/ 64 <10000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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};
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};
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bus_lcd0: bus-lcd0 {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK200>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus: bus-leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus-mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_peri: bus-peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peri_opp_table>;
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status = "disabled";
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bus_peri_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-5000000 {
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opp-hz = /bits/ 64 <5000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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};
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bus_rightbus: bus-rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@900 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x900>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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clock-latency = <160000>;
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operating-points = <
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1200000 1250000
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1000000 1150000
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800000 1075000
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500000 975000
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400000 975000
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200000 950000
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>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@901 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x901>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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clock-latency = <160000>;
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operating-points = <
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1200000 1250000
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1000000 1150000
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800000 1075000
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500000 975000
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400000 975000
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200000 950000
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>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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bus_leftbus_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-suspend;
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};
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};
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soc: soc {
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sysram: sram@2020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x20000>;
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smp-sram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sram@1f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x1f000 0x1000>;
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};
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};
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pd_lcd1: power-domain@10023ca0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023ca0 0x20>;
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#power-domain-cells = <0>;
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label = "LCD1";
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};
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l2c: cache-controller@10502000 {
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compatible = "arm,pl310-cache";
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reg = <0x10502000 0x1000>;
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cache-unified;
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cache-level = <2>;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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arm,tag-latency = <2 2 1>;
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arm,data-latency = <2 2 1>;
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};
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mct: timer@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<&combiner 12 6>,
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<&combiner 12 7>,
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<&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog: watchdog@10060000 {
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compatible = "samsung,s3c6410-wdt";
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reg = <0x10060000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_WDT>;
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clock-names = "watchdog";
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_2: pinctrl@3860000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x03860000 0x1000>;
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};
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g2d: g2d@12800000 {
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compatible = "samsung,s5pv210-g2d";
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reg = <0x12800000 0x1000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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power-domains = <&pd_lcd0>;
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iommus = <&sysmmu_g2d>;
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};
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ppmu_acp: ppmu@10ae0000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10ae0000 0x2000>;
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status = "disabled";
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};
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ppmu_lcd1: ppmu@12240000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x12240000 0x2000>;
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clocks = <&clock CLK_PPMULCD1>;
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clock-names = "ppmu";
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status = "disabled";
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};
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sysmmu_g2d: sysmmu@12a20000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12a20000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 7>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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power-domains = <&pd_lcd0>;
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#iommu-cells = <0>;
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};
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sysmmu_fimd1: sysmmu@12220000 {
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compatible = "samsung,exynos-sysmmu";
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interrupt-parent = <&combiner>;
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reg = <0x12220000 0x1000>;
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interrupts = <5 3>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
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power-domains = <&pd_lcd1>;
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#iommu-cells = <0>;
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};
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};
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};
|
||
|
|
|
||
|
|
&cpu_alert0 {
|
||
|
|
temperature = <85000>; /* millicelsius */
|
||
|
|
};
|
||
|
|
|
||
|
|
&cpu_alert1 {
|
||
|
|
temperature = <100000>; /* millicelsius */
|
||
|
|
};
|
||
|
|
|
||
|
|
&cpu_alert2 {
|
||
|
|
temperature = <110000>; /* millicelsius */
|
||
|
|
};
|
||
|
|
|
||
|
|
&cpu_thermal {
|
||
|
|
polling-delay-passive = <0>;
|
||
|
|
polling-delay = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&gic {
|
||
|
|
cpu-offset = <0x8000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&camera {
|
||
|
|
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
|
||
|
|
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
|
||
|
|
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
|
||
|
|
};
|
||
|
|
|
||
|
|
&combiner {
|
||
|
|
samsung,combiner-nr = <16>;
|
||
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&fimc_0 {
|
||
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
||
|
|
samsung,mainscaler-ext;
|
||
|
|
samsung,cam-if;
|
||
|
|
};
|
||
|
|
|
||
|
|
&fimc_1 {
|
||
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
||
|
|
samsung,mainscaler-ext;
|
||
|
|
samsung,cam-if;
|
||
|
|
};
|
||
|
|
|
||
|
|
&fimc_2 {
|
||
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
||
|
|
samsung,mainscaler-ext;
|
||
|
|
samsung,lcd-wb;
|
||
|
|
};
|
||
|
|
|
||
|
|
&fimc_3 {
|
||
|
|
samsung,pix-limits = <1920 8192 1366 1920>;
|
||
|
|
samsung,rotators = <0>;
|
||
|
|
samsung,mainscaler-ext;
|
||
|
|
samsung,lcd-wb;
|
||
|
|
};
|
||
|
|
|
||
|
|
&gpu {
|
||
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "gp",
|
||
|
|
"gpmmu",
|
||
|
|
"pp0",
|
||
|
|
"ppmmu0",
|
||
|
|
"pp1",
|
||
|
|
"ppmmu1",
|
||
|
|
"pp2",
|
||
|
|
"ppmmu2",
|
||
|
|
"pp3",
|
||
|
|
"ppmmu3";
|
||
|
|
operating-points-v2 = <&gpu_opp_table>;
|
||
|
|
|
||
|
|
gpu_opp_table: opp-table {
|
||
|
|
compatible = "operating-points-v2";
|
||
|
|
|
||
|
|
opp-160000000 {
|
||
|
|
opp-hz = /bits/ 64 <160000000>;
|
||
|
|
opp-microvolt = <950000>;
|
||
|
|
};
|
||
|
|
opp-267000000 {
|
||
|
|
opp-hz = /bits/ 64 <267000000>;
|
||
|
|
opp-microvolt = <1050000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&mdma1 {
|
||
|
|
power-domains = <&pd_lcd0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&mixer {
|
||
|
|
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
|
||
|
|
"sclk_mixer";
|
||
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||
|
|
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
|
||
|
|
<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&pmu {
|
||
|
|
interrupts = <2 2>, <3 2>;
|
||
|
|
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pmu_system_controller {
|
||
|
|
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||
|
|
"clkout4", "clkout8", "clkout9";
|
||
|
|
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
||
|
|
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
||
|
|
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&rotator {
|
||
|
|
power-domains = <&pd_lcd0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&sysmmu_rotator {
|
||
|
|
power-domains = <&pd_lcd0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&tmu {
|
||
|
|
compatible = "samsung,exynos4210-tmu";
|
||
|
|
clocks = <&clock CLK_TMU_APBIF>;
|
||
|
|
clock-names = "tmu_apbif";
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "exynos4210-pinctrl.dtsi"
|