794 lines
19 KiB
Plaintext
794 lines
19 KiB
Plaintext
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/*
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* Copyright 2017 Gateworks Corporation
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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chosen {
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stdout-path = &uart2;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000>;
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brightness-levels = <
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0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100
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>;
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default-brightness-level = <100>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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user-pb {
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label = "user_pb";
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gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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interrupts = <0>;
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};
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key-erased {
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label = "key-erased";
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linux,code = <BTN_2>;
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interrupt-parent = <&gsc>;
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interrupts = <1>;
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};
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eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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tamper {
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label = "tamper";
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linux,code = <BTN_4>;
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interrupt-parent = <&gsc>;
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interrupts = <5>;
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};
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switch-hold {
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label = "switch_hold";
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linux,code = <BTN_5>;
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interrupt-parent = <&gsc>;
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interrupts = <7>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led0: led-user1 {
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label = "user1";
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gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
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default-state = "off";
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};
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};
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x40000000>;
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};
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reg_5p0v: regulator-5p0v {
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compatible = "regulator-fixed";
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regulator-name = "5P0V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_2p5v: regulator-2p5v {
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compatible = "regulator-fixed";
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regulator-name = "2P5V";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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reg_usb_h1_vbus: regulator-usb-h1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 30 0>;
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enable-active-high;
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_12p0: regulator-12p0v {
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compatible = "regulator-fixed";
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regulator-name = "12P0V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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sound {
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compatible = "fsl,imx-audio-tlv320";
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model = "imx-tlv320";
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ssi-controller = <&ssi1>;
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audio-codec = <&tlv320aic3105>;
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/* routing of sink, source */
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audio-routing =
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/* TLV320 LINE1L pin <-> Mic Jack connector */
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"LINE1L", "Mic Jack",
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/* board Headphone Jack <-> HPOUT */
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"Mic Jack", "Mic Bias";
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mux-int-port = <1>;
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mux-ext-port = <6>;
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};
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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interrupt-parent = <&gpio1>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#size-cells = <0>;
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adc {
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compatible = "gw,gsc-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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gw,mode = <0>;
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reg = <0x00>;
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label = "temp";
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};
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channel@2 {
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gw,mode = <1>;
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reg = <0x02>;
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label = "vdd_vin";
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};
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channel@5 {
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gw,mode = <1>;
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reg = <0x05>;
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label = "vdd_3p3";
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};
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channel@8 {
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gw,mode = <1>;
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reg = <0x08>;
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label = "vdd_bat";
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};
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channel@b {
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gw,mode = <1>;
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reg = <0x0b>;
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label = "vdd_5p0";
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};
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channel@e {
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gw,mode = <1>;
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reg = <0xe>;
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label = "vdd_arm";
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};
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channel@11 {
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gw,mode = <1>;
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reg = <0x11>;
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label = "vdd_soc";
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};
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channel@14 {
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gw,mode = <1>;
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reg = <0x14>;
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label = "vdd_3p0";
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};
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channel@17 {
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gw,mode = <1>;
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reg = <0x17>;
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label = "vdd_1p5";
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};
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channel@1d {
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gw,mode = <1>;
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reg = <0x1d>;
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label = "vdd_1p8";
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};
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channel@20 {
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gw,mode = <1>;
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reg = <0x20>;
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label = "vdd_an1";
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};
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channel@23 {
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gw,mode = <1>;
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reg = <0x23>;
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label = "vdd_2p5";
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};
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};
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};
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gsc_gpio: gpio@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gsc>;
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interrupts = <4>;
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};
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eeprom1: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom2: eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom3: eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom4: eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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dts1672: rtc@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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ltc3676: pmic@3c {
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compatible = "lltc,ltc3676";
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reg = <0x3c>;
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interrupt-parent = <&gpio1>;
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interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
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regulators {
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/* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
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reg_1p8v: sw1 {
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regulator-name = "vdd1p8";
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regulator-min-microvolt = <1033310>;
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regulator-max-microvolt = <2004000>;
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lltc,fb-voltage-divider = <301000 200000>;
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regulator-ramp-delay = <7000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_DDR (1+R1/R2 = 2.105) */
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reg_vdd_ddr: sw2 {
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regulator-name = "vddddr";
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regulator-min-microvolt = <868310>;
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regulator-max-microvolt = <1684000>;
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lltc,fb-voltage-divider = <221000 200000>;
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|
|
regulator-ramp-delay = <7000>;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* VDD_ARM (1+R1/R2 = 1.635) */
|
||
|
|
reg_vdd_arm: sw3 {
|
||
|
|
regulator-name = "vddarm";
|
||
|
|
regulator-min-microvolt = <674400>;
|
||
|
|
regulator-max-microvolt = <1308000>;
|
||
|
|
lltc,fb-voltage-divider = <127000 200000>;
|
||
|
|
regulator-ramp-delay = <7000>;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
linux,phandle = <®_vdd_arm>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* VDD_SOC (1+R1/R2 = 1.635) */
|
||
|
|
reg_vdd_soc: sw4 {
|
||
|
|
regulator-name = "vddsoc";
|
||
|
|
regulator-min-microvolt = <674400>;
|
||
|
|
regulator-max-microvolt = <1308000>;
|
||
|
|
lltc,fb-voltage-divider = <127000 200000>;
|
||
|
|
regulator-ramp-delay = <7000>;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
linux,phandle = <®_vdd_soc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* VDD_1P0 (1+R1/R2 = 1.38): */
|
||
|
|
reg_1p0v: ldo2 {
|
||
|
|
regulator-name = "vdd1p0";
|
||
|
|
regulator-min-microvolt = <1002777>;
|
||
|
|
regulator-max-microvolt = <1002777>;
|
||
|
|
lltc,fb-voltage-divider = <100000 261000>;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* VDD_HIGH (1+R1/R2 = 4.17) */
|
||
|
|
reg_3p0v: ldo4 {
|
||
|
|
regulator-name = "vdd3p0";
|
||
|
|
regulator-min-microvolt = <3023250>;
|
||
|
|
regulator-max-microvolt = <3023250>;
|
||
|
|
lltc,fb-voltage-divider = <634000 200000>;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c3 {
|
||
|
|
clock-frequency = <400000>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
tlv320aic3105: codec@18 {
|
||
|
|
compatible = "ti,tlv320aic3x";
|
||
|
|
reg = <0x18>;
|
||
|
|
reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
|
||
|
|
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||
|
|
ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
|
||
|
|
/* Regulators */
|
||
|
|
DRVDD-supply = <®_3p3v>;
|
||
|
|
AVDD-supply = <®_3p3v>;
|
||
|
|
IOVDD-supply = <®_3p3v>;
|
||
|
|
DVDD-supply = <®_1p8v>;
|
||
|
|
};
|
||
|
|
|
||
|
|
accelerometer@1d {
|
||
|
|
compatible = "fsl,mma8451";
|
||
|
|
reg = <0x1d>;
|
||
|
|
interrupt-parent = <&gpio7>;
|
||
|
|
interrupts = <11 IRQ_TYPE_EDGE_RISING>;
|
||
|
|
interrupt-names = "INT2";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* headphone detect */
|
||
|
|
ts3a227e@3b {
|
||
|
|
compatible = "ti,ts3a227e";
|
||
|
|
reg = <0x3b>;
|
||
|
|
interrupt-parent = <&gpio5>;
|
||
|
|
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||
|
|
ti,micbias = <4>; /* 2.5V micbias */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&ldb {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
lvds-channel@0 {
|
||
|
|
fsl,data-mapping = "spwg";
|
||
|
|
fsl,data-width = <18>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
display-timings {
|
||
|
|
native-mode = <&timing0>;
|
||
|
|
timing0: g101evn010 {
|
||
|
|
clock-frequency = <68930000>;
|
||
|
|
hactive = <1280>;
|
||
|
|
vactive = <800>;
|
||
|
|
hback-porch = <220>;
|
||
|
|
hfront-porch = <40>;
|
||
|
|
vback-porch = <21>;
|
||
|
|
vfront-porch = <7>;
|
||
|
|
hsync-len = <60>;
|
||
|
|
vsync-len = <10>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm1 {
|
||
|
|
#pwm-cells = <2>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&ssi1 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart2 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usbotg {
|
||
|
|
vbus-supply = <®_usb_otg_vbus>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
||
|
|
disable-over-current;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usbh1 {
|
||
|
|
vbus-supply = <®_usb_h1_vbus>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
|
||
|
|
vmmc-supply = <®_3p3v>;
|
||
|
|
non-removable;
|
||
|
|
bus-width = <4>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc2 {
|
||
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
||
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||
|
|
cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
|
||
|
|
vmmc-supply = <®_3p3v>;
|
||
|
|
max-frequency = <100000000>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc3 {
|
||
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
||
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||
|
|
non-removable;
|
||
|
|
vmmc-supply = <®_3p3v>;
|
||
|
|
keep-power-in-suspend;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&wdog1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
||
|
|
fsl,ext-reset-output;
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc {
|
||
|
|
pinctrl_audmux: audmuxgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
|
||
|
|
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
|
||
|
|
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
|
||
|
|
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
|
||
|
|
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet: enetgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||
|
|
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
|
||
|
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||
|
|
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
/* I2C3 */
|
||
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||
|
|
|
||
|
|
/* Headphone Detect */
|
||
|
|
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */
|
||
|
|
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */
|
||
|
|
|
||
|
|
/* Codec */
|
||
|
|
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */
|
||
|
|
|
||
|
|
/* Touch Controller */
|
||
|
|
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */
|
||
|
|
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */
|
||
|
|
|
||
|
|
/* Stow Sensor */
|
||
|
|
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */
|
||
|
|
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm1: pwm1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg: usbotggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
||
|
|
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */
|
||
|
|
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */
|
||
|
|
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */
|
||
|
|
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */
|
||
|
|
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */
|
||
|
|
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */
|
||
|
|
|
||
|
|
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9
|
||
|
|
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||
|
|
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */
|
||
|
|
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
|
||
|
|
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */
|
||
|
|
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
|
||
|
|
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */
|
||
|
|
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||
|
|
MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||
|
|
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|