558 lines
12 KiB
Plaintext
558 lines
12 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2018 Protonic Holland
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* Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx6qp.dtsi"
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/ {
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model = "Protonic WD3 board";
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compatible = "prt,prtwd3", "fsl,imx6qp";
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chosen {
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stdout-path = &uart4;
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};
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x20000000>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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clock_ksz8081: clock-ksz8081 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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clock_ksz9031: clock-ksz9031 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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clock_mcp251xfd: clock-mcp251xfd {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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};
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clock_sja1105: clock-sja1105 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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mdio {
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compatible = "virtual,mdio-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
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&gpio5 7 GPIO_ACTIVE_HIGH>;
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/* Microchip KSZ8081 */
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usbeth_phy: ethernet-phy@3 {
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reg = <0x3>;
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interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500>;
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reset-deassert-us = <1000>;
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clocks = <&clock_ksz8081>;
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clock-names = "rmii-ref";
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micrel,led-mode = <0>;
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};
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tja1102_phy0: ethernet-phy@4 {
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reg = <0x4>;
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interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <20>;
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reset-deassert-us = <2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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tja1102_phy1: ethernet-phy@5 {
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reg = <0x5>;
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interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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reg_5v0: regulator-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_otg_vbus: regulator-otg-vbus {
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compatible = "regulator-fixed";
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regulator-name = "otg-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi_npd>;
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reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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xceiver-supply = <®_5v0>;
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status = "okay";
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};
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&ecspi2 {
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cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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status = "okay";
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switch@0 {
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compatible = "nxp,sja1105q";
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reg = <0>;
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spi-max-frequency = <4000000>;
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spi-rx-delay-us = <1>;
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spi-tx-delay-us = <1>;
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spi-cpha;
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reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
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clocks = <&clock_sja1105>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "usb";
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phy-handle = <&usbeth_phy>;
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phy-mode = "rmii";
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};
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port@1 {
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reg = <1>;
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label = "t1slave";
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phy-handle = <&tja1102_phy1>;
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phy-mode = "rmii";
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};
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port@2 {
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reg = <2>;
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label = "t1master";
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phy-handle = <&tja1102_phy0>;
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phy-mode = "rmii";
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};
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port@3 {
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reg = <3>;
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label = "rj45";
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phy-handle = <&rgmii_phy>;
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phy-mode = "rgmii-id";
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&fec>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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};
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};
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&ecspi3 {
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cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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status = "okay";
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can@0 {
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compatible = "microchip,mcp251xfd";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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reg = <0>;
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clocks = <&clock_mcp251xfd>;
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spi-max-frequency = <10000000>;
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interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
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assigned-clock-rates = <125000000>;
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status = "okay";
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phy-mode = "rgmii";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Microchip KSZ9031 */
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rgmii_phy: ethernet-phy@2 {
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reg = <2>;
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interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <1000>;
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clocks = <&clock_ksz9031>;
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};
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};
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};
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&gpio1 {
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gpio-line-names =
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"", "SD1_CD", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "PHY3_RESET", "", "", "PHY3_INT", "", "", "";
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};
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&gpio2 {
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gpio-line-names =
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"", "", "", "", "", "", "", "",
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"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3",
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"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
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"", "", "", "", "", "", "", "",
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"", "", "ECSPI2_SS0", "", "", "", "", "";
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};
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&gpio3 {
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gpio-line-names =
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "", "", "", "", "",
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"", "", "", "", "CAN1_SR", "CAN2_SR", "", "",
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"", "", "", "", "", "", "", "",
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"ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", "";
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};
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&gpio5 {
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gpio-line-names =
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"", "", "", "", "", "SW_RESET", "", "",
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"PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET",
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"PHY0_INT", "", "", "",
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"", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD",
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"", "",
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"", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ",
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"DISP0_EN", "CAM_GPIO0";
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};
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&gpio6 {
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gpio-line-names =
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"LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD",
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"CAM_LOCK", "", "POWER_TG",
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"POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "",
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"USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1",
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"USB_ETH_CHG_ID2", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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/* additional i2c devices are added automatically by the boot loader */
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};
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&i2c3 {
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adc@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* VIN */
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channel@4 {
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reg = <4>;
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ti,gain = <1>;
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ti,datarate = <3>;
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};
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/* VBUS */
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channel@5 {
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reg = <5>;
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ti,gain = <1>;
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ti,datarate = <3>;
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};
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/* ICHG */
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channel@6 {
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reg = <6>;
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ti,gain = <1>;
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ti,datarate = <3>;
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};
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channel@7 {
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reg = <7>;
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ti,gain = <1>;
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ti,datarate = <3>;
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};
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};
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usbotg {
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vbus-supply = <®_otg_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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phy_type = "utmi";
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&usbphynop1 {
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status = "disabled";
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};
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&usbphynop2 {
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status = "disabled";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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disable-wp;
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cap-sd-highspeed;
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no-mmc;
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no-sdio;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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non-removable;
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mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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brcmf: bcrmf@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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&usdhc3 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
||
|
|
bus-width = <8>;
|
||
|
|
no-1-8-v;
|
||
|
|
non-removable;
|
||
|
|
no-sd;
|
||
|
|
no-sdio;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc {
|
||
|
|
pinctrl_can1: can1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
|
||
|
|
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
|
||
|
|
/* CAN1_SR */
|
||
|
|
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_can2: can2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
/* CAN2_nINT */
|
||
|
|
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
|
||
|
|
/* CAN2_SR */
|
||
|
|
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi2: ecspi2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
|
||
|
|
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
|
||
|
|
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
|
||
|
|
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi3: ecspi3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||
|
|
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||
|
|
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||
|
|
/* CS */
|
||
|
|
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet: enetgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||
|
|
|
||
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
|
||
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
|
||
|
|
|
||
|
|
/* Configure clock provider for RGMII ref clock */
|
||
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
|
||
|
|
/* Configure clock consumer for RGMII ref clock */
|
||
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
|
||
|
|
|
||
|
|
/* SJA1105Q switch reset */
|
||
|
|
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030
|
||
|
|
|
||
|
|
/* phy3/rgmii_phy reset */
|
||
|
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030
|
||
|
|
/* phy3/rgmii_phy int */
|
||
|
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
|
||
|
|
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_mdio: mdiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
/* phy0/usbeth_phy reset */
|
||
|
|
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030
|
||
|
|
/* phy0/usbeth_phy int */
|
||
|
|
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
|
||
|
|
|
||
|
|
/* phy12/tja1102_phy0 reset */
|
||
|
|
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030
|
||
|
|
/* phy12/tja1102_phy0 int */
|
||
|
|
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1
|
||
|
|
/* phy12/tja1102_phy0 enable. Set 100K pull-up */
|
||
|
|
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart4: uart4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg: usbotggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
|
||
|
|
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
|
||
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
|
||
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
|
||
|
|
MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wifi_npd: wifinpd {
|
||
|
|
fsl,pins = <
|
||
|
|
/* WL_REG_ON */
|
||
|
|
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|