364 lines
8.2 KiB
Plaintext
364 lines
8.2 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/clock/qcom,lcc-msm8960.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm MSM8960";
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compatible = "qcom,msm8960";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_PPI 14 0x304>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <GIC_PPI 10 0x304>;
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qcom,no-pc-write;
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};
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clocks {
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cxo_board: cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "cxo_board";
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};
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pxo_board: pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "pxo_board";
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "sleep_clk";
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};
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};
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/* Temporary fixed regulator */
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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regulator-always-on;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
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"qcom,msm-timer";
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interrupts = <GIC_PPI 1 0x301>,
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<GIC_PPI 2 0x301>,
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<GIC_PPI 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>;
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cpu-offset = <0x80000>;
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};
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msmgpio: pinctrl@800000 {
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compatible = "qcom,msm8960-pinctrl";
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gpio-controller;
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gpio-ranges = <&msmgpio 0 0 152>;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800000 0x4000>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8960";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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clocks = <&cxo_board>,
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<&pxo_board>,
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<&lcc PLL4>;
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clock-names = "cxo", "pxo", "pll4";
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};
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lcc: clock-controller@28000000 {
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compatible = "qcom,lcc-msm8960";
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reg = <0x28000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&pxo_board>,
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<&gcc PLL4_VOTE>,
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<0>,
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<0>, <0>,
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<0>, <0>,
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<0>;
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clock-names = "pxo",
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"pll4_vote",
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"mi2s_codec_clk",
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"codec_i2s_mic_codec_clk",
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"spare_i2s_mic_codec_clk",
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"codec_i2s_spkr_codec_clk",
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"spare_i2s_spkr_codec_clk",
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"pcm_codec_clk";
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};
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clock-controller@4000000 {
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compatible = "qcom,mmcc-msm8960";
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reg = <0x4000000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&pxo_board>,
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<&gcc PLL3>,
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<&gcc PLL8_VOTE>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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clock-names = "pxo",
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"pll3",
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"pll8_vote",
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"dsi1pll",
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"dsi1pllbyte",
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"dsi2pll",
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"dsi2pllbyte",
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"hdmipll";
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};
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l2cc: clock-controller@2011000 {
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compatible = "qcom,kpss-gcc", "syscon";
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reg = <0x2011000 0x1000>;
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};
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rpm: rpm@108000 {
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compatible = "qcom,rpm-msm8960";
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reg = <0x108000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack", "err", "wakeup";
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regulators {
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compatible = "qcom,rpm-pm8921-regulators";
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};
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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compatible = "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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gsbi5: gsbi@16400000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <5>;
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reg = <0x16400000 0x100>;
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clocks = <&gcc GSBI5_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi5_serial: serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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<0x16400000 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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pmicintc: pmic {
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compatible = "qcom,pm8921";
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interrupt-parent = <&msmgpio>;
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interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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pwrkey@1c {
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compatible = "qcom,pm8921-pwrkey";
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reg = <0x1c>;
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interrupt-parent = <&pmicintc>;
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interrupts = <50 IRQ_TYPE_EDGE_RISING>,
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<51 IRQ_TYPE_EDGE_RISING>;
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debounce = <15625>;
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pull-up;
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};
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keypad@148 {
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compatible = "qcom,pm8921-keypad";
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reg = <0x148>;
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interrupt-parent = <&pmicintc>;
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interrupts = <74 IRQ_TYPE_EDGE_RISING>,
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<75 IRQ_TYPE_EDGE_RISING>;
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debounce = <15>;
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scan-delay = <32>;
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row-hold = <91500>;
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};
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rtc@11d {
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compatible = "qcom,pm8921-rtc";
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interrupt-parent = <&pmicintc>;
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interrupts = <39 IRQ_TYPE_EDGE_RISING>;
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reg = <0x11d>;
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allow-set-time;
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};
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};
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};
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rng@1a500000 {
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compatible = "qcom,prng";
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reg = <0x1a500000 0x200>;
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clocks = <&gcc PRNG_CLK>;
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clock-names = "core";
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};
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sdcc3: mmc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x8000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <192000000>;
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no-1-8-v;
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vmmc-supply = <&vsdcc_fixed>;
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};
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sdcc1: mmc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x8000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-msm8960", "syscon";
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reg = <0x1a400000 0x100>;
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};
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gsbi1: gsbi@16000000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <1>;
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reg = <0x16000000 0x100>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gsbi1_spi: spi@16080000 {
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compatible = "qcom,spi-qup-v1.1.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x16080000 0x1000>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <24000000>;
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cs-gpios = <&msmgpio 8 0>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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};
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};
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