80 lines
1.7 KiB
Plaintext
80 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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/dts-v1/;
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#include "rv1126.dtsi"
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#include "rv1126-edgeble-neu2.dtsi"
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/ {
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model = "Edgeble Neu2 IO Board";
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compatible = "edgeble,neural-compute-module-2-io",
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"edgeble,neural-compute-module-2", "rockchip,rv1126";
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aliases {
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serial2 = &uart2;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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};
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&gmac {
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assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
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<&cru CLK_GMAC_ETHERNET_OUT>;
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assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
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assigned-clock-rates = <125000000>, <0>, <25000000>;
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clock_in_out = "input";
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phy-handle = <&phy>;
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phy-mode = "rgmii";
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phy-supply = <&vcc_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
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tx_delay = <0x2a>;
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rx_delay = <0x1a>;
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status = "okay";
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};
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&mdio {
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phy: ethernet-phy@0 {
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compatible = "ethernet-phy-id001c.c916",
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"ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <ð_phy_rst>;
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reset-assert-us = <20000>;
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reset-deassert-us = <100000>;
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reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
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};
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};
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&pinctrl {
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ethernet {
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eth_phy_rst: eth-phy-rst {
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rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&sdmmc {
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr104;
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vqmmc-supply = <&vccio_sd>;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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