139 lines
5.1 KiB
C
139 lines
5.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/hardware/dec21285.h
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*
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* Copyright (C) 1998 Russell King
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*
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* DC21285 registers
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*/
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#define DC21285_PCI_IACK 0x79000000
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#define DC21285_ARMCSR_BASE 0x42000000
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#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
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#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
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#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
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#define DC21285_FLASH 0x41000000
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#define DC21285_PCI_IO 0x7c000000
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#define DC21285_PCI_MEM 0x80000000
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#ifndef __ASSEMBLY__
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#include <mach/hardware.h>
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#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
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#else
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#define DC21285_IO(x) (x)
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#endif
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/*
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* The footbridge is programmed to expose the system RAM at 0xe0000000.
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* The requirement is that the RAM isn't placed at bus address 0, which
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* would clash with VGA cards.
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*/
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#define BUS_OFFSET 0xe0000000
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#define CSR_PCICMD DC21285_IO(0x0004)
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#define CSR_CLASSREV DC21285_IO(0x0008)
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#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
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#define CSR_PCICSRBASE DC21285_IO(0x0010)
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#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
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#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
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#define CSR_PCIROMBASE DC21285_IO(0x0030)
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#define CSR_MBOX0 DC21285_IO(0x0050)
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#define CSR_MBOX1 DC21285_IO(0x0054)
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#define CSR_MBOX2 DC21285_IO(0x0058)
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#define CSR_MBOX3 DC21285_IO(0x005c)
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#define CSR_DOORBELL DC21285_IO(0x0060)
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#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
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#define CSR_ROMWRITEREG DC21285_IO(0x0068)
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#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
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#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
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#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
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#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
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#define CSR_ROMBASEMASK DC21285_IO(0x0108)
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#define CSR_SDRAMTIMING DC21285_IO(0x010c)
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#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
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#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
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#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
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#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
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#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
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#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
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#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
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#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
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#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
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#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
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#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
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#define CSR_SA110_CNTL DC21285_IO(0x013c)
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#define SA110_CNTL_INITCMPLETE (1 << 0)
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#define SA110_CNTL_ASSERTSERR (1 << 1)
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#define SA110_CNTL_RXSERR (1 << 3)
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#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
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#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
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#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
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#define SA110_CNTL_DISCARDTIMER (1 << 8)
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#define SA110_CNTL_PCINRESET (1 << 9)
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#define SA110_CNTL_I2O_256 (0 << 10)
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#define SA110_CNTL_I20_512 (1 << 10)
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#define SA110_CNTL_I2O_1024 (2 << 10)
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#define SA110_CNTL_I2O_2048 (3 << 10)
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#define SA110_CNTL_I2O_4096 (4 << 10)
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#define SA110_CNTL_I2O_8192 (5 << 10)
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#define SA110_CNTL_I2O_16384 (6 << 10)
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#define SA110_CNTL_I2O_32768 (7 << 10)
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#define SA110_CNTL_WATCHDOG (1 << 13)
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#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
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#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
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#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
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#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
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#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
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#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
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#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
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#define SA110_CNTL_XCSDIR(x) ((x)<<28)
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#define SA110_CNTL_PCICFN (1 << 31)
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#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
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#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
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#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
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#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
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#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
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#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
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#define CSR_UARTDR DC21285_IO(0x0160)
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#define CSR_RXSTAT DC21285_IO(0x0164)
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#define CSR_H_UBRLCR DC21285_IO(0x0168)
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#define CSR_M_UBRLCR DC21285_IO(0x016c)
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#define CSR_L_UBRLCR DC21285_IO(0x0170)
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#define CSR_UARTCON DC21285_IO(0x0174)
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#define CSR_UARTFLG DC21285_IO(0x0178)
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#define CSR_IRQ_STATUS DC21285_IO(0x0180)
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#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
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#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
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#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
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#define CSR_IRQ_SOFT DC21285_IO(0x0190)
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#define CSR_FIQ_STATUS DC21285_IO(0x0280)
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#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
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#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
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#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
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#define CSR_FIQ_SOFT DC21285_IO(0x0290)
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#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
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#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
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#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
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#define CSR_TIMER1_CLR DC21285_IO(0x030c)
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#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
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#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
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#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
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#define CSR_TIMER2_CLR DC21285_IO(0x032c)
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#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
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#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
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#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
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#define CSR_TIMER3_CLR DC21285_IO(0x034c)
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#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
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#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
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#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
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#define CSR_TIMER4_CLR DC21285_IO(0x036c)
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#define TIMER_CNTL_ENABLE (1 << 7)
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#define TIMER_CNTL_AUTORELOAD (1 << 6)
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#define TIMER_CNTL_DIV1 (0)
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#define TIMER_CNTL_DIV16 (1 << 2)
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#define TIMER_CNTL_DIV256 (2 << 2)
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#define TIMER_CNTL_CNTEXT (3 << 2)
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