70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/kernel/opcodes.c
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*
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* A32 condition code lookup feature moved from nwfpe/fpopcode.c
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*/
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#include <linux/module.h>
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#include <asm/opcodes.h>
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#define ARM_OPCODE_CONDITION_UNCOND 0xf
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/*
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* condition code lookup table
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* index into the table is test code: EQ, NE, ... LT, GT, AL, NV
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*
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* bit position in short is condition code: NZCV
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*/
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static const unsigned short cc_map[16] = {
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0xF0F0, /* EQ == Z set */
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0x0F0F, /* NE */
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0xCCCC, /* CS == C set */
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0x3333, /* CC */
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0xFF00, /* MI == N set */
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0x00FF, /* PL */
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0xAAAA, /* VS == V set */
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0x5555, /* VC */
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0x0C0C, /* HI == C set && Z clear */
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0xF3F3, /* LS == C clear || Z set */
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0xAA55, /* GE == (N==V) */
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0x55AA, /* LT == (N!=V) */
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0x0A05, /* GT == (!Z && (N==V)) */
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0xF5FA, /* LE == (Z || (N!=V)) */
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0xFFFF, /* AL always */
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0 /* NV */
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};
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/*
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* Returns:
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* ARM_OPCODE_CONDTEST_FAIL - if condition fails
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* ARM_OPCODE_CONDTEST_PASS - if condition passes (including AL)
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* ARM_OPCODE_CONDTEST_UNCOND - if NV condition, or separate unconditional
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* opcode space from v5 onwards
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*
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* Code that tests whether a conditional instruction would pass its condition
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* check should check that return value == ARM_OPCODE_CONDTEST_PASS.
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*
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* Code that tests if a condition means that the instruction would be executed
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* (regardless of conditional or unconditional) should instead check that the
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* return value != ARM_OPCODE_CONDTEST_FAIL.
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*/
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asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)
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{
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u32 cc_bits = opcode >> 28;
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u32 psr_cond = psr >> 28;
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unsigned int ret;
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if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
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if ((cc_map[cc_bits] >> (psr_cond)) & 1)
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ret = ARM_OPCODE_CONDTEST_PASS;
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else
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ret = ARM_OPCODE_CONDTEST_FAIL;
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} else {
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ret = ARM_OPCODE_CONDTEST_UNCOND;
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(arm_check_condition);
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