395 lines
9.7 KiB
Plaintext
395 lines
9.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-a100-ccu.h>
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#include <dt-bindings/clock/sun50i-a100-r-ccu.h>
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#include <dt-bindings/reset/sun50i-a100-ccu.h>
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#include <dt-bindings/reset/sun50i-a100-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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dcxo24M: dcxo24M-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "dcxo24M";
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#clock-cells = <0>;
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};
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iosc: internal-osc-clk {
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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#clock-cells = <0>;
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};
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osc32k: osc32k-clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x3fffffff>;
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-a100-ccu";
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reg = <0x03001000 0x1000>;
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clocks = <&dcxo24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun50i-a100-dma";
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reg = <0x03002000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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resets = <&ccu RST_BUS_DMA>;
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dma-channels = <8>;
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dma-requests = <52>;
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#dma-cells = <1>;
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
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<0x03024000 0x2000>, <0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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efuse@3006000 {
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compatible = "allwinner,sun50i-a100-sid",
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"allwinner,sun50i-a64-sid";
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reg = <0x03006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ths_calibration: calib@14 {
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reg = <0x14 8>;
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};
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-a100-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB9", "PB10";
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function = "uart0";
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};
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};
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@5000400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000400 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@5000800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000800 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@5000c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000c00 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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uart4: serial@5001000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05001000 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART4>;
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resets = <&ccu RST_BUS_UART4>;
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status = "disabled";
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};
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i2c0: i2c@5002000 {
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compatible = "allwinner,sun50i-a100-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x05002000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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dmas = <&dma 43>, <&dma 43>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@5002400 {
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compatible = "allwinner,sun50i-a100-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x05002400 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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dmas = <&dma 44>, <&dma 44>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@5002800 {
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compatible = "allwinner,sun50i-a100-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x05002800 0x400>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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dmas = <&dma 45>, <&dma 45>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c3: i2c@5002c00 {
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compatible = "allwinner,sun50i-a100-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x05002c00 0x400>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C3>;
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resets = <&ccu RST_BUS_I2C3>;
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dmas = <&dma 46>, <&dma 46>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ths: thermal-sensor@5070400 {
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compatible = "allwinner,sun50i-a100-ths";
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reg = <0x05070400 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_THS>;
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clock-names = "bus";
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resets = <&ccu RST_BUS_THS>;
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nvmem-cells = <&ths_calibration>;
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nvmem-cell-names = "calibration";
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#thermal-sensor-cells = <1>;
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};
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r_ccu: clock@7010000 {
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compatible = "allwinner,sun50i-a100-r-ccu";
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reg = <0x07010000 0x300>;
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clocks = <&dcxo24M>, <&osc32k>, <&iosc>,
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<&ccu CLK_PLL_PERIPH0>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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r_intc: interrupt-controller@7010320 {
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compatible = "allwinner,sun50i-a100-nmi",
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"allwinner,sun9i-a80-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x07010320 0xc>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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r_pio: pinctrl@7022000 {
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compatible = "allwinner,sun50i-a100-r-pinctrl";
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reg = <0x07022000 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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r_i2c0_pins: r-i2c0-pins {
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pins = "PL0", "PL1";
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function = "s_i2c0";
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};
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r_i2c1_pins: r-i2c1-pins {
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pins = "PL8", "PL9";
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function = "s_i2c1";
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};
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};
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r_uart: serial@7080000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07080000 0x400>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&r_ccu CLK_R_APB2_UART>;
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resets = <&r_ccu RST_R_APB2_UART>;
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status = "disabled";
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};
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r_i2c0: i2c@7081400 {
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compatible = "allwinner,sun50i-a100-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x07081400 0x400>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB2_I2C0>;
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resets = <&r_ccu RST_R_APB2_I2C0>;
|
||
|
|
dmas = <&dma 50>, <&dma 50>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&r_i2c0_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
r_i2c1: i2c@7081800 {
|
||
|
|
compatible = "allwinner,sun50i-a100-i2c",
|
||
|
|
"allwinner,sun8i-v536-i2c",
|
||
|
|
"allwinner,sun6i-a31-i2c";
|
||
|
|
reg = <0x07081800 0x400>;
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&r_ccu CLK_R_APB2_I2C1>;
|
||
|
|
resets = <&r_ccu RST_R_APB2_I2C1>;
|
||
|
|
dmas = <&dma 51>, <&dma 51>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&r_i2c1_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
thermal-zones {
|
||
|
|
cpu-thermal {
|
||
|
|
polling-delay-passive = <0>;
|
||
|
|
polling-delay = <0>;
|
||
|
|
thermal-sensors = <&ths 0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ddr-thermal {
|
||
|
|
polling-delay-passive = <0>;
|
||
|
|
polling-delay = <0>;
|
||
|
|
thermal-sensors = <&ths 2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu-thermal {
|
||
|
|
polling-delay-passive = <0>;
|
||
|
|
polling-delay = <0>;
|
||
|
|
thermal-sensors = <&ths 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|