358 lines
8.6 KiB
Plaintext
358 lines
8.6 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2019-2021 TQ-Systems GmbH
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*/
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#include "imx8mq.dtsi"
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/ {
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model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
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compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";
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memory@40000000 {
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device_type = "memory";
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/* our minimum RAM config will be 1024 MiB */
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reg = <0x00000000 0x40000000 0 0x40000000>;
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};
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/* e-MMC IO, needed for HS modes */
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reg_vcc1v8: regulator-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "TQMA8MX_VCC1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_vcc3v3: regulator-vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "TQMA8MX_VCC3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_vdd_arm: regulator-vdd-arm {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dvfs>;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "TQMa8Mx_DVFS";
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regulator-type = "voltage";
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regulator-settling-time-us = <150000>;
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gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
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states = <900000 0x1 1000000 0x0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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/* 640 MiB */
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size = <0 0x28000000>;
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/* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
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alloc-ranges = <0 0x40000000 0 0x78000000>;
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linux,cma-default;
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};
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};
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};
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&A53_0 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_1 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_2 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_3 {
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cpu-supply = <®_vdd_arm>;
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};
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&gpu {
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status = "okay";
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};
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&pgc_gpu {
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power-supply = <&sw1a_reg>;
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};
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&pgc_vpu {
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power-supply = <&sw1c_reg>;
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pfuze100: pmic@8 {
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compatible = "fsl,pfuze100";
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fsl,pfuze-support-disable-sw;
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reg = <0x8>;
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regulators {
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/* VDD_GPU */
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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/* VDD_VPU */
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sw1c_reg: sw1c {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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/* NVCC_DRAM */
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sw2_reg: sw2 {
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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/* VDD_DRAM */
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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/* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
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nvcc_1v8_reg: sw4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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/* not used */
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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/* VDD_PHY_0V9 */
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <975000>;
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regulator-always-on;
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};
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/* VDD_PHY_1V8 */
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1675000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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/* VDDA_1V8 */
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1625000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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/* VDD_PHY_3V3 */
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <3075000>;
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regulator-max-microvolt = <3625000>;
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regulator-always-on;
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};
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/* not used */
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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sensor0: temperature-sensor@1b {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1b>;
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};
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pcf85063: rtc@51 {
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compatible = "nxp,pcf85063a";
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reg = <0x51>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc>;
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interrupt-parent = <&gpio1>;
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interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
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quartz-load-femtofarads = <7000>;
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clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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eeprom1: eeprom@53 {
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compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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read-only;
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vcc-supply = <®_vcc3v3>;
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};
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eeprom0: eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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vcc-supply = <®_vcc3v3>;
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};
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};
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&pcie0 {
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/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
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vph-supply = <&vgen5_reg>;
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};
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&pcie1 {
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/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
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vph-supply = <&vgen5_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <84000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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no-sd;
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no-sdio;
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vmmc-supply = <®_vcc3v3>;
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vqmmc-supply = <®_vcc1v8>;
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status = "okay";
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};
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/* Attention: wdog reset forcing POR needs baseboard support */
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&wdog1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_dvfs: dvfsgrp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>,
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<MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>;
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};
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pinctrl_i2c1_gpio: i2c1gpiogrp {
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fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>,
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<MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>,
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<MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
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<MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>,
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<MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>,
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<MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>,
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<MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>;
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};
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pinctrl_rtc: rtcgrp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>,
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<MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>,
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<MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>,
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<MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>,
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<MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>,
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<MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>,
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<MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>,
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<MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>,
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<MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>,
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<MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>,
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<MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>,
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<MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>,
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<MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>,
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<MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>,
|
||
|
|
<MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;
|
||
|
|
};
|
||
|
|
};
|