388 lines
7.9 KiB
Plaintext
388 lines
7.9 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for MACCHIATOBin Armada 8040 community board platform
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*/
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#include "armada-8040.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell 8040 MACCHIATOBin";
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compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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aliases {
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp1_eth0;
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ethernet2 = &cp1_eth1;
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ethernet3 = &cp1_eth2;
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};
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/* Regulator labels correspond with schematics */
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v_3_3: regulator-3-3v {
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compatible = "regulator-fixed";
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regulator-name = "v_3_3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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status = "okay";
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};
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v_vddo_h: regulator-1-8v {
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compatible = "regulator-fixed";
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regulator-name = "v_vddo_h";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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status = "okay";
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};
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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status = "okay";
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};
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sfp_eth0: sfp-eth0 {
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/* CON15,16 - CPM lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp0_i2c>;
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los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
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tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp0_pins>;
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maximum-power-milliwatt = <2000>;
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};
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sfp_eth1: sfp-eth1 {
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/* CON17,18 - CPS lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp1_i2c>;
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los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
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tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
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maximum-power-milliwatt = <2000>;
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};
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sfp_eth3: sfp-eth3 {
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/* CON13,14 - CPS lane 5 */
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compatible = "sff,sfp";
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i2c-bus = <&sfp_1g_i2c>;
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los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
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tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
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maximum-power-milliwatt = <2000>;
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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&ap_sdhci0 {
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bus-width = <8>;
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/*
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* Not stable in HS modes - phy needs "more calibration", so add
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* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
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*/
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marvell,xenon-phy-slow-mode;
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no-1-8-v;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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vqmmc-supply = <&v_vddo_h>;
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};
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&cp0_i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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};
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&cp0_i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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i2c-switch@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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sfpp0_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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sfpp1_i2c: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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sfp_1g_i2c: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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};
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};
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/* J25 UART header */
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&cp0_uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_uart1_pins>;
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status = "okay";
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};
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&cp0_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_ge_mdio_pins>;
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status = "okay";
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ge_phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp0_pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_pcie_pins>;
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num-lanes = <4>;
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num-viewport = <8>;
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reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
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ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
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phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
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<&cp0_comphy2 0>, <&cp0_comphy3 0>;
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phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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"cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
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status = "okay";
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};
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&cp0_pinctrl {
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cp0_ge_mdio_pins: ge-mdio-pins {
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marvell,pins = "mpp32", "mpp34";
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marvell,function = "ge";
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};
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cp0_i2c1_pins: i2c1-pins {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_i2c0_pins: i2c0-pins {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_uart1_pins: uart1-pins {
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marvell,pins = "mpp40", "mpp41";
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marvell,function = "uart1";
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};
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cp0_xhci_vbus_pins: xhci0-vbus-pins {
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cp0_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp51", "mpp53", "mpp54";
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marvell,function = "gpio";
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};
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cp0_pcie_pins: pcie-pins {
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marvell,pins = "mpp52";
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marvell,function = "gpio";
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};
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cp0_sdhci_pins: sdhci-pins {
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marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
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"mpp60", "mpp61";
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marvell,function = "sdio";
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};
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cp0_sfpp1_pins: sfpp1-pins {
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marvell,pins = "mpp62";
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marvell,function = "gpio";
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy4 0>;
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};
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&cp0_sata0 {
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status = "okay";
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/* CPM Lane 5 - U29 */
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sata-port@1 {
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phys = <&cp0_comphy5 1>;
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phy-names = "cp0-sata0-1-phy";
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};
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};
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&cp0_sdhci0 {
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/* U6 */
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broken-cd;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins>;
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status = "okay";
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vqmmc-supply = <&v_3_3>;
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};
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&cp0_utmi {
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status = "okay";
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};
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&cp0_usb3_0 {
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/* J38? - USB2.0 only */
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phys = <&cp0_utmi0>;
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phy-names = "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&cp0_usb3_1 {
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/* J38? - USB2.0 only */
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phys = <&cp0_utmi1>;
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phy-names = "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&cp1_ethernet {
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status = "okay";
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};
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&cp1_eth0 {
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy4 0>;
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};
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&cp1_eth1 {
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/* CPS Lane 0 - J5 (Gigabit RJ45) */
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status = "okay";
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/* Network PHY */
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phy = <&ge_phy>;
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phy-mode = "sgmii";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy0 1>;
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};
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&cp1_eth2 {
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/* CPS Lane 5 */
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status = "okay";
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/* Network PHY */
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phy-mode = "2500base-x";
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managed = "in-band-status";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy5 2>;
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sfp = <&sfp_eth3>;
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};
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&cp1_pinctrl {
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cp1_sfpp1_pins: sfpp1-pins {
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marvell,pins = "mpp8", "mpp10", "mpp11";
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marvell,function = "gpio";
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};
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cp1_spi1_pins: spi1-pins {
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marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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cp1_uart0_pins: uart0-pins {
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marvell,pins = "mpp6", "mpp7";
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marvell,function = "uart0";
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};
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cp1_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp24";
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marvell,function = "gpio";
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};
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cp1_sfpp0_pins: sfpp0-pins {
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marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
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marvell,function = "gpio";
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};
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};
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/* J27 UART header */
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&cp1_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_uart0_pins>;
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status = "okay";
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};
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&cp1_sata0 {
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status = "okay";
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/* CPS Lane 1 - U32 */
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sata-port@0 {
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phys = <&cp1_comphy1 0>;
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phy-names = "cp1-sata0-0-phy";
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};
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/* CPS Lane 3 - U31 */
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sata-port@1 {
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phys = <&cp1_comphy3 1>;
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phy-names = "cp1-sata0-1-phy";
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};
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};
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&cp1_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_spi1_pins>;
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status = "okay";
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flash@0 {
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compatible = "st,w25q32";
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spi-max-frequency = <50000000>;
|
||
|
|
reg = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_comphy2 {
|
||
|
|
cp1_usbh0_con: connector {
|
||
|
|
compatible = "usb-a-connector";
|
||
|
|
phy-supply = <&v_5v0_usb3_hst_vbus>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_utmi {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_usb3_0 {
|
||
|
|
/* CPS Lane 2 - CON7 */
|
||
|
|
phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
|
||
|
|
phy-names = "cp1-usb3h0-comphy", "utmi";
|
||
|
|
dr_mode = "host";
|
||
|
|
status = "okay";
|
||
|
|
};
|