266 lines
7.4 KiB
Plaintext
266 lines
7.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "rk356x.dtsi"
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/ {
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compatible = "rockchip,rk3568";
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sata0: sata@fc000000 {
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compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
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reg = <0 0xfc000000 0 0x1000>;
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clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
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<&cru CLK_SATA0_RXOOB>;
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clock-names = "sata", "pmalive", "rxoob";
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&combphy0 PHY_TYPE_SATA>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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power-domains = <&power RK3568_PD_PIPE>;
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status = "disabled";
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};
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pipe_phy_grf0: syscon@fdc70000 {
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compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
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reg = <0x0 0xfdc70000 0x0 0x1000>;
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};
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qos_pcie3x1: qos@fe190080 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe190080 0x0 0x20>;
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};
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qos_pcie3x2: qos@fe190100 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe190100 0x0 0x20>;
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};
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qos_sata0: qos@fe190200 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe190200 0x0 0x20>;
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};
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pcie30_phy_grf: syscon@fdcb8000 {
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compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfdcb8000 0x0 0x10000>;
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};
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pcie30phy: phy@fe8c0000 {
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compatible = "rockchip,rk3568-pcie3-phy";
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reg = <0x0 0xfe8c0000 0x0 0x20000>;
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#phy-cells = <0>;
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clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
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<&cru PCLK_PCIE30PHY>;
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clock-names = "refclk_m", "refclk_n", "pclk";
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resets = <&cru SRST_PCIE30PHY>;
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reset-names = "phy";
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rockchip,phy-grf = <&pcie30_phy_grf>;
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status = "disabled";
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};
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pcie3x1: pcie@fe270000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
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<0 0 0 2 &pcie3x1_intc 1>,
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<0 0 0 3 &pcie3x1_intc 2>,
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<0 0 0 4 &pcie3x1_intc 3>;
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linux,pci-domain = <1>;
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x1000 0x1000>;
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num-lanes = <1>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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reg = <0x3 0xc0400000 0x0 0x00400000>,
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<0x0 0xfe270000 0x0 0x00010000>,
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<0x3 0x7f000000 0x0 0x01000000>;
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ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
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<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE30X1_POWERUP>;
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reset-names = "pipe";
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/* bifurcation; lane1 when using 1+1 */
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status = "disabled";
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pcie3x1_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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<0 0 0 2 &pcie3x2_intc 1>,
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<0 0 0 3 &pcie3x2_intc 2>,
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<0 0 0 4 &pcie3x2_intc 3>;
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linux,pci-domain = <2>;
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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reg = <0x3 0xc0800000 0x0 0x00400000>,
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<0x0 0xfe280000 0x0 0x00010000>,
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<0x3 0xbf000000 0x0 0x01000000>;
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ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
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<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE30X2_POWERUP>;
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reset-names = "pipe";
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/* bifurcation; lane0 when using 1+1 */
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status = "disabled";
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pcie3x2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
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};
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};
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gmac0: ethernet@fe2a0000 {
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compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe2a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq";
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clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
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<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
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<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
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<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_refout",
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"aclk_mac", "pclk_mac",
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"clk_mac_speed", "ptp_ref";
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resets = <&cru SRST_A_GMAC0>;
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reset-names = "stmmaceth";
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rockchip,grf = <&grf>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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snps,mixed-burst;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,tso;
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <0 0 0 0 16 8 4>;
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snps,rd_osr_lmt = <8>;
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snps,wr_osr_lmt = <4>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {};
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};
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};
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combphy0: phy@fe820000 {
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compatible = "rockchip,rk3568-naneng-combphy";
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reg = <0x0 0xfe820000 0x0 0x100>;
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clocks = <&pmucru CLK_PCIEPHY0_REF>,
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<&cru PCLK_PIPEPHY0>,
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<&cru PCLK_PIPE>;
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clock-names = "ref", "apb", "pipe";
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assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PIPEPHY0>;
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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#phy-cells = <1>;
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status = "disabled";
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};
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};
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&cpu0_opp_table {
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opp-1992000000 {
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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};
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};
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&pipegrf {
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compatible = "rockchip,rk3568-pipe-grf", "syscon";
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};
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&power {
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power-domain@RK3568_PD_PIPE {
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reg = <RK3568_PD_PIPE>;
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clocks = <&cru PCLK_PIPE>;
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pm_qos = <&qos_pcie2x1>,
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<&qos_pcie3x1>,
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<&qos_pcie3x2>,
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<&qos_sata0>,
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<&qos_sata1>,
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<&qos_sata2>,
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<&qos_usb3_0>,
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<&qos_usb3_1>;
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#power-domain-cells = <0>;
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};
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};
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&usb_host0_xhci {
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phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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&vop {
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compatible = "rockchip,rk3568-vop";
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};
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