76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_HYP_FAULT_H__
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#define __ARM64_KVM_HYP_FAULT_H__
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)
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{
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u64 par, tmp;
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/*
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* Resolve the IPA the hard way using the guest VA.
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*
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* Stage-1 translation already validated the memory access
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* rights. As such, we can use the EL1 translation regime, and
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* don't have to distinguish between EL0 and EL1 access.
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*
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* We do need to save/restore PAR_EL1 though, as we haven't
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* saved the guest context yet, and we may return early...
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*/
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par = read_sysreg_par();
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if (!__kvm_at("s1e1r", far))
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tmp = read_sysreg_par();
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else
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tmp = SYS_PAR_EL1_F; /* back to the guest */
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write_sysreg(par, par_el1);
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if (unlikely(tmp & SYS_PAR_EL1_F))
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return false; /* Translation failed, back to guest */
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/* Convert PAR to HPFAR format */
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*hpfar = PAR_TO_HPFAR(tmp);
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return true;
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}
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static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)
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{
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u64 hpfar, far;
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far = read_sysreg_el2(SYS_FAR);
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/*
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* The HPFAR can be invalid if the stage 2 fault did not
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* happen during a stage 1 page table walk (the ESR_EL2.S1PTW
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* bit is clear) and one of the two following cases are true:
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* 1. The fault was due to a permission fault
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* 2. The processor carries errata 834220
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*
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* Therefore, for all non S1PTW faults where we either have a
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* permission fault or the errata workaround is enabled, we
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* resolve the IPA using the AT instruction.
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*/
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if (!(esr & ESR_ELx_S1PTW) &&
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(cpus_have_final_cap(ARM64_WORKAROUND_834220) ||
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(esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_PERM)) {
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if (!__translate_far_to_hpfar(far, &hpfar))
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return false;
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} else {
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hpfar = read_sysreg(hpfar_el2);
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}
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fault->far_el2 = far;
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fault->hpfar_el2 = hpfar;
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return true;
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}
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#endif
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