224 lines
6.2 KiB
C
224 lines
6.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_IA64_ATOMIC_H
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#define _ASM_IA64_ATOMIC_H
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* NOTE: don't mess with the types below! The "unsigned long" and
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* "int" types were carefully placed so as to ensure proper operation
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* of the macros.
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*
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* Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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#include <linux/types.h>
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#include <asm/intrinsics.h>
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#include <asm/barrier.h>
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#define ATOMIC64_INIT(i) { (i) }
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#define arch_atomic_read(v) READ_ONCE((v)->counter)
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#define arch_atomic64_read(v) READ_ONCE((v)->counter)
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#define arch_atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
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#define arch_atomic64_set(v,i) WRITE_ONCE(((v)->counter), (i))
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#define ATOMIC_OP(op, c_op) \
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static __inline__ int \
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ia64_atomic_##op (int i, atomic_t *v) \
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{ \
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__s32 old, new; \
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CMPXCHG_BUGCHECK_DECL \
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\
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do { \
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CMPXCHG_BUGCHECK(v); \
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old = arch_atomic_read(v); \
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new = old c_op i; \
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} while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \
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return new; \
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}
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#define ATOMIC_FETCH_OP(op, c_op) \
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static __inline__ int \
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ia64_atomic_fetch_##op (int i, atomic_t *v) \
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{ \
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__s32 old, new; \
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CMPXCHG_BUGCHECK_DECL \
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\
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do { \
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CMPXCHG_BUGCHECK(v); \
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old = arch_atomic_read(v); \
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new = old c_op i; \
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} while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \
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return old; \
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}
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#define ATOMIC_OPS(op, c_op) \
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ATOMIC_OP(op, c_op) \
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ATOMIC_FETCH_OP(op, c_op)
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ATOMIC_OPS(add, +)
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ATOMIC_OPS(sub, -)
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#ifdef __OPTIMIZE__
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#define __ia64_atomic_const(i) \
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static const int __ia64_atomic_p = __builtin_constant_p(i) ? \
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((i) == 1 || (i) == 4 || (i) == 8 || (i) == 16 || \
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(i) == -1 || (i) == -4 || (i) == -8 || (i) == -16) : 0;\
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__ia64_atomic_p
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#else
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#define __ia64_atomic_const(i) 0
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#endif
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#define arch_atomic_add_return(i,v) \
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({ \
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int __ia64_aar_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
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: ia64_atomic_add(__ia64_aar_i, v); \
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})
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#define arch_atomic_sub_return(i,v) \
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({ \
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int __ia64_asr_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
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: ia64_atomic_sub(__ia64_asr_i, v); \
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})
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#define arch_atomic_fetch_add(i,v) \
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({ \
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int __ia64_aar_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \
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: ia64_atomic_fetch_add(__ia64_aar_i, v); \
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})
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#define arch_atomic_fetch_sub(i,v) \
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({ \
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int __ia64_asr_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \
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: ia64_atomic_fetch_sub(__ia64_asr_i, v); \
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})
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ATOMIC_FETCH_OP(and, &)
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ATOMIC_FETCH_OP(or, |)
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ATOMIC_FETCH_OP(xor, ^)
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#define arch_atomic_and(i,v) (void)ia64_atomic_fetch_and(i,v)
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#define arch_atomic_or(i,v) (void)ia64_atomic_fetch_or(i,v)
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#define arch_atomic_xor(i,v) (void)ia64_atomic_fetch_xor(i,v)
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#define arch_atomic_fetch_and(i,v) ia64_atomic_fetch_and(i,v)
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#define arch_atomic_fetch_or(i,v) ia64_atomic_fetch_or(i,v)
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#define arch_atomic_fetch_xor(i,v) ia64_atomic_fetch_xor(i,v)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP
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#define ATOMIC64_OP(op, c_op) \
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static __inline__ s64 \
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ia64_atomic64_##op (s64 i, atomic64_t *v) \
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{ \
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s64 old, new; \
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CMPXCHG_BUGCHECK_DECL \
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\
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do { \
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CMPXCHG_BUGCHECK(v); \
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old = arch_atomic64_read(v); \
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new = old c_op i; \
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} while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \
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return new; \
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}
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#define ATOMIC64_FETCH_OP(op, c_op) \
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static __inline__ s64 \
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ia64_atomic64_fetch_##op (s64 i, atomic64_t *v) \
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{ \
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s64 old, new; \
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CMPXCHG_BUGCHECK_DECL \
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\
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do { \
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CMPXCHG_BUGCHECK(v); \
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old = arch_atomic64_read(v); \
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new = old c_op i; \
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} while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \
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return old; \
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}
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#define ATOMIC64_OPS(op, c_op) \
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ATOMIC64_OP(op, c_op) \
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ATOMIC64_FETCH_OP(op, c_op)
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ATOMIC64_OPS(add, +)
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ATOMIC64_OPS(sub, -)
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#define arch_atomic64_add_return(i,v) \
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({ \
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s64 __ia64_aar_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
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: ia64_atomic64_add(__ia64_aar_i, v); \
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})
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#define arch_atomic64_sub_return(i,v) \
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({ \
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s64 __ia64_asr_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
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: ia64_atomic64_sub(__ia64_asr_i, v); \
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})
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#define arch_atomic64_fetch_add(i,v) \
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({ \
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s64 __ia64_aar_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \
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: ia64_atomic64_fetch_add(__ia64_aar_i, v); \
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})
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#define arch_atomic64_fetch_sub(i,v) \
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({ \
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s64 __ia64_asr_i = (i); \
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__ia64_atomic_const(i) \
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? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \
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: ia64_atomic64_fetch_sub(__ia64_asr_i, v); \
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})
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ATOMIC64_FETCH_OP(and, &)
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ATOMIC64_FETCH_OP(or, |)
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ATOMIC64_FETCH_OP(xor, ^)
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#define arch_atomic64_and(i,v) (void)ia64_atomic64_fetch_and(i,v)
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#define arch_atomic64_or(i,v) (void)ia64_atomic64_fetch_or(i,v)
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#define arch_atomic64_xor(i,v) (void)ia64_atomic64_fetch_xor(i,v)
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#define arch_atomic64_fetch_and(i,v) ia64_atomic64_fetch_and(i,v)
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#define arch_atomic64_fetch_or(i,v) ia64_atomic64_fetch_or(i,v)
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#define arch_atomic64_fetch_xor(i,v) ia64_atomic64_fetch_xor(i,v)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP
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#define arch_atomic_cmpxchg(v, old, new) (arch_cmpxchg(&((v)->counter), old, new))
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#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new))
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#define arch_atomic64_cmpxchg(v, old, new) \
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(arch_cmpxchg(&((v)->counter), old, new))
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#define arch_atomic64_xchg(v, new) (arch_xchg(&((v)->counter), new))
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#define arch_atomic_add(i,v) (void)arch_atomic_add_return((i), (v))
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#define arch_atomic_sub(i,v) (void)arch_atomic_sub_return((i), (v))
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#define arch_atomic64_add(i,v) (void)arch_atomic64_add_return((i), (v))
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#define arch_atomic64_sub(i,v) (void)arch_atomic64_sub_return((i), (v))
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#endif /* _ASM_IA64_ATOMIC_H */
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