138 lines
4.8 KiB
C
138 lines
4.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Bit definitions for the MCF54xx ACR and CACR registers.
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*/
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#ifndef m54xxacr_h
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#define m54xxacr_h
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/*
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* Define the Cache register flags.
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*/
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#define CACR_DEC 0x80000000 /* Enable data cache */
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#define CACR_DWP 0x40000000 /* Data write protection */
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#define CACR_DESB 0x20000000 /* Enable data store buffer */
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#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
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#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
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#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
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#define CACR_DDCM_P 0x04000000 /* No cache, precise */
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#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
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#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
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#define CACR_BEC 0x00080000 /* Enable branch cache */
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#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
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#define CACR_IEC 0x00008000 /* Enable instruction cache */
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#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
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#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
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#define CACR_IHLCK 0x00000800 /* Instruction cache half lock */
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#define CACR_IDCM 0x00000400 /* Instruction cache inhibit */
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#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
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#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
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#define ACR_BASE_POS 24 /* Address Base */
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#define ACR_MASK_POS 16 /* Address Mask */
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#define ACR_ENABLE 0x00008000 /* Enable address */
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#define ACR_USER 0x00000000 /* User mode access only */
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#define ACR_SUPER 0x00002000 /* Supervisor mode only */
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#define ACR_ANY 0x00004000 /* Match any access mode */
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#define ACR_CM_WT 0x00000000 /* Write through mode */
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#define ACR_CM_CP 0x00000020 /* Copyback mode */
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#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
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#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
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#define ACR_CM 0x00000060 /* Cache mode mask */
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#define ACR_SP 0x00000008 /* Supervisor protect */
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#define ACR_WPROTECT 0x00000004 /* Write protect */
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#define ACR_BA(x) ((x) & 0xff000000)
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#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
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#if defined(CONFIG_M5407)
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#define ICACHE_SIZE 0x4000 /* instruction - 16k */
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#define DCACHE_SIZE 0x2000 /* data - 8k */
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#elif defined(CONFIG_M54xx)
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#define ICACHE_SIZE 0x8000 /* instruction - 32k */
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#define DCACHE_SIZE 0x8000 /* data - 32k */
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#elif defined(CONFIG_M5441x)
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#define ICACHE_SIZE 0x2000 /* instruction - 8k */
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#define DCACHE_SIZE 0x2000 /* data - 8k */
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#endif
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#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
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#define CACHE_WAYS 4 /* 4 ways */
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#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
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#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
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#define ICACHE_MAX_ADDR ICACHE_SET_MASK
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#define DCACHE_MAX_ADDR DCACHE_SET_MASK
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/*
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* Version 4 cores have a true harvard style separate instruction
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* and data cache. Enable data and instruction caches, also enable write
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* buffers and branch accelerator.
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*/
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/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
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/* use '+' instead of '|' for assembler's sake */
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/* Enable data cache */
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/* Enable data store buffer */
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/* outside ACRs : No cache, precise */
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/* Enable instruction+branch caches */
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#if defined(CONFIG_M5407)
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#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
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#else
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#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
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#endif
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#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
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#if defined(CONFIG_MMU)
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/*
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* If running with the MMU enabled then we need to map the internal
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* register region as non-cacheable. And then we map all our RAM as
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* cacheable and supervisor access only.
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*/
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#define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
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#if defined(CONFIG_CACHE_COPYBACK)
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#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
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#else
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#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
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#endif
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#define ACR2_MODE 0
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#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP)
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#else
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/*
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* For the non-MMU enabled case we map all of RAM as cacheable.
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*/
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#if defined(CONFIG_CACHE_COPYBACK)
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#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
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#else
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#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
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#endif
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#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
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#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
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#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
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#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
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#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
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#define ACR1_MODE 0
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#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
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#define ACR3_MODE 0
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#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
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/* Copyback cache mode must push dirty cache lines first */
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#define CACHE_PUSH
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#endif
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#endif /* CONFIG_MMU */
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#endif /* m54xxacr_h */
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