431 lines
8.4 KiB
Plaintext
431 lines
8.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/ingenic,tcu.h>
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#include <dt-bindings/clock/ingenic,x1830-cgu.h>
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#include <dt-bindings/dma/x1830-dma.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ingenic,x1830";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "ingenic,xburst-fpu2.0-mxu2.0";
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reg = <0>;
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clocks = <&cgu X1830_CLK_CPU>;
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clock-names = "cpu";
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};
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: interrupt-controller@10001000 {
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compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
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reg = <0x10001000 0x50>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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exclk: ext {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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rtclk: rtc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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cgu: x1830-cgu@10000000 {
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compatible = "ingenic,x1830-cgu", "simple-mfd";
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reg = <0x10000000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10000000 0x100>;
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#clock-cells = <1>;
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clocks = <&exclk>, <&rtclk>;
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clock-names = "ext", "rtc";
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otg_phy: usb-phy@3c {
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compatible = "ingenic,x1830-phy";
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reg = <0x3c 0x10>;
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clocks = <&cgu X1830_CLK_OTGPHY>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mac_phy_ctrl: mac-phy-ctrl@e8 {
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compatible = "syscon";
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reg = <0xe8 0x4>;
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};
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};
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ost: timer@12000000 {
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compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
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reg = <0x12000000 0x3c>;
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#clock-cells = <1>;
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clocks = <&cgu X1830_CLK_OST>;
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clock-names = "ost";
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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};
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tcu: timer@10002000 {
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compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
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reg = <0x10002000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10002000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu X1830_CLK_RTCLK>,
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<&cgu X1830_CLK_EXCLK>,
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<&cgu X1830_CLK_PCLK>,
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<&cgu X1830_CLK_TCU>;
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clock-names = "rtc", "ext", "pclk", "tcu";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <27 26 25>;
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wdt: watchdog@0 {
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compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
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reg = <0x0 0x10>;
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clocks = <&tcu TCU_CLK_WDT>;
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clock-names = "wdt";
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};
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pwm: pwm@40 {
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compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
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reg = <0x40 0x80>;
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#pwm-cells = <3>;
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clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
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<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
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<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
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<&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
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clock-names = "timer0", "timer1", "timer2", "timer3",
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"timer4", "timer5", "timer6", "timer7";
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};
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};
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rtc: rtc@10003000 {
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compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
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reg = <0x10003000 0x4c>;
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interrupt-parent = <&intc>;
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interrupts = <32>;
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clocks = <&cgu X1830_CLK_RTCLK>;
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clock-names = "rtc";
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};
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pinctrl: pin-controller@10010000 {
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compatible = "ingenic,x1830-pinctrl";
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reg = <0x10010000 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpa: gpio@0 {
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compatible = "ingenic,x1830-gpio";
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reg = <0>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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gpb: gpio@1 {
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compatible = "ingenic,x1830-gpio";
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reg = <1>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 32 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <16>;
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};
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gpc: gpio@2 {
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compatible = "ingenic,x1830-gpio";
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reg = <2>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 64 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <15>;
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};
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gpd: gpio@3 {
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compatible = "ingenic,x1830-gpio";
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reg = <3>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 96 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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};
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};
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uart0: serial@10030000 {
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compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
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reg = <0x10030000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <51>;
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clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
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clock-names = "baud", "module";
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status = "disabled";
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};
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uart1: serial@10031000 {
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compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
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reg = <0x10031000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <50>;
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clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
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clock-names = "baud", "module";
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status = "disabled";
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};
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ssi0: spi@10043000 {
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compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
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reg = <0x10043000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <9>;
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clocks = <&cgu X1830_CLK_SSI0>;
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clock-names = "spi";
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dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
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<&pdma X1830_DMA_SSI0_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ssi1: spi@10044000 {
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compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
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reg = <0x10044000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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clocks = <&cgu X1830_CLK_SSI1>;
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clock-names = "spi";
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dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
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<&pdma X1830_DMA_SSI1_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c0: i2c-controller@10050000 {
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compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
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reg = <0x10050000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <60>;
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clocks = <&cgu X1830_CLK_SMB0>;
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status = "disabled";
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};
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i2c1: i2c-controller@10051000 {
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compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
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reg = <0x10051000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <59>;
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clocks = <&cgu X1830_CLK_SMB1>;
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status = "disabled";
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};
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i2c2: i2c-controller@10052000 {
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compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
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reg = <0x10052000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <58>;
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clocks = <&cgu X1830_CLK_SMB2>;
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status = "disabled";
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};
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dtrng: trng@10072000 {
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compatible = "ingenic,x1830-dtrng";
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reg = <0x10072000 0xc>;
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clocks = <&cgu X1830_CLK_DTRNG>;
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status = "disabled";
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};
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pdma: dma-controller@13420000 {
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compatible = "ingenic,x1830-dma";
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reg = <0x13420000 0x400>, <0x13421000 0x40>;
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#dma-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <10>;
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clocks = <&cgu X1830_CLK_PDMA>;
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};
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msc0: mmc@13450000 {
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compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
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reg = <0x13450000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <37>;
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clocks = <&cgu X1830_CLK_MSC0>;
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clock-names = "mmc";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
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<&pdma X1830_DMA_MSC0_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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msc1: mmc@13460000 {
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compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
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reg = <0x13460000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <36>;
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clocks = <&cgu X1830_CLK_MSC1>;
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clock-names = "mmc";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
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<&pdma X1830_DMA_MSC1_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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mac: ethernet@134b0000 {
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compatible = "ingenic,x1830-mac", "snps,dwmac";
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reg = <0x134b0000 0x2000>;
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interrupt-parent = <&intc>;
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interrupts = <55>;
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interrupt-names = "macirq";
|
||
|
|
|
||
|
|
clocks = <&cgu X1830_CLK_MAC>;
|
||
|
|
clock-names = "stmmaceth";
|
||
|
|
|
||
|
|
mode-reg = <&mac_phy_ctrl>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
mdio: mdio {
|
||
|
|
compatible = "snps,dwmac-mdio";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
otg: usb@13500000 {
|
||
|
|
compatible = "ingenic,x1830-otg";
|
||
|
|
reg = <0x13500000 0x40000>;
|
||
|
|
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
interrupts = <21>;
|
||
|
|
|
||
|
|
clocks = <&cgu X1830_CLK_OTG>;
|
||
|
|
clock-names = "otg";
|
||
|
|
|
||
|
|
phys = <&otg_phy>;
|
||
|
|
phy-names = "usb2-phy";
|
||
|
|
|
||
|
|
g-rx-fifo-size = <768>;
|
||
|
|
g-np-tx-fifo-size = <256>;
|
||
|
|
g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|