240 lines
5.9 KiB
C
240 lines
5.9 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
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* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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* IP32 changes by Ilya.
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* Copyright (C) 2010 Cavium Networks, Inc.
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*/
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#include <linux/dma-direct.h>
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#include <linux/memblock.h>
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#include <linux/swiotlb.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/bootinfo.h>
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#include <asm/octeon/octeon.h>
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#ifdef CONFIG_PCI
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#include <linux/pci.h>
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#include <asm/octeon/pci-octeon.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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struct octeon_dma_map_ops {
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dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
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phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
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};
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static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
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{
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if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
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return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
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else
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return paddr;
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}
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static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
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{
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if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
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return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
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else
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return daddr;
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}
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static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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return octeon_hole_phys_to_dma(paddr);
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}
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static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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daddr = octeon_hole_dma_to_phys(daddr);
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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static const struct octeon_dma_map_ops octeon_gen1_ops = {
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.phys_to_dma = octeon_gen1_phys_to_dma,
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.dma_to_phys = octeon_gen1_dma_to_phys,
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};
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static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return octeon_hole_phys_to_dma(paddr);
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}
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static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return octeon_hole_dma_to_phys(daddr);
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}
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static const struct octeon_dma_map_ops octeon_gen2_ops = {
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.phys_to_dma = octeon_gen2_phys_to_dma,
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.dma_to_phys = octeon_gen2_dma_to_phys,
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};
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static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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/* Anything in the BAR1 hole or above goes via BAR2 */
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if (paddr >= 0xf0000000ull)
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paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
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return paddr;
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}
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static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
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daddr -= OCTEON_BAR2_PCI_ADDRESS;
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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static const struct octeon_dma_map_ops octeon_big_ops = {
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.phys_to_dma = octeon_big_phys_to_dma,
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.dma_to_phys = octeon_big_dma_to_phys,
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};
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static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
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phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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/* Anything not in the BAR1 range goes via BAR2 */
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if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
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paddr = paddr - octeon_bar1_pci_phys;
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else
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paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
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return paddr;
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}
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static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
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dma_addr_t daddr)
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{
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if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
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daddr -= OCTEON_BAR2_PCI_ADDRESS;
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else
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daddr += octeon_bar1_pci_phys;
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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static const struct octeon_dma_map_ops octeon_small_ops = {
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.phys_to_dma = octeon_small_phys_to_dma,
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.dma_to_phys = octeon_small_dma_to_phys,
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};
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static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
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void __init octeon_pci_dma_init(void)
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{
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switch (octeon_dma_bar_type) {
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case OCTEON_DMA_BAR_TYPE_PCIE:
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octeon_pci_dma_ops = &octeon_gen1_ops;
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break;
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case OCTEON_DMA_BAR_TYPE_PCIE2:
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octeon_pci_dma_ops = &octeon_gen2_ops;
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break;
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case OCTEON_DMA_BAR_TYPE_BIG:
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octeon_pci_dma_ops = &octeon_big_ops;
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break;
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case OCTEON_DMA_BAR_TYPE_SMALL:
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octeon_pci_dma_ops = &octeon_small_ops;
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break;
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default:
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BUG();
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}
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}
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#endif /* CONFIG_PCI */
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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#ifdef CONFIG_PCI
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if (dev && dev_is_pci(dev))
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return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
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#endif
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return paddr;
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}
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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#ifdef CONFIG_PCI
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if (dev && dev_is_pci(dev))
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return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
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#endif
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return daddr;
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}
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void __init plat_swiotlb_setup(void)
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{
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phys_addr_t start, end;
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phys_addr_t max_addr;
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phys_addr_t addr_size;
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size_t swiotlbsize;
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u64 i;
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max_addr = 0;
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addr_size = 0;
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for_each_mem_range(i, &start, &end) {
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/* These addresses map low for PCI. */
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if (start > 0x410000000ull && !OCTEON_IS_OCTEON2())
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continue;
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addr_size += (end - start);
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if (max_addr < end)
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max_addr = end;
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}
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swiotlbsize = PAGE_SIZE;
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#ifdef CONFIG_PCI
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/*
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* For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
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* size to a maximum of 64MB
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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|| OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
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swiotlbsize = addr_size / 4;
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if (swiotlbsize > 64 * (1<<20))
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swiotlbsize = 64 * (1<<20);
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} else if (max_addr > 0xf0000000ul) {
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/*
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* Otherwise only allocate a big iotlb if there is
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* memory past the BAR1 hole.
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*/
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swiotlbsize = 64 * (1<<20);
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}
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#endif
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#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
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/* OCTEON II ohci is only 32-bit. */
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if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
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swiotlbsize = 64 * (1<<20);
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#endif
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swiotlb_adjust_size(swiotlbsize);
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swiotlb_init(true, SWIOTLB_VERBOSE);
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}
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