141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Utility functions to decode Octeon's RSL_INT_BLOCKS
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* interrupts into error messages.
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-asxx-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#ifndef PRINT_ERROR
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#define PRINT_ERROR(format, ...)
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#endif
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void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
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/**
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* Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
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* CN58XX.
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*
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* @block: Interface to enable 0-1
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*/
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void __cvmx_interrupt_asxx_enable(int block)
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{
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int mask;
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union cvmx_asxx_int_en csr;
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/*
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* CN38XX and CN58XX have two interfaces with 4 ports per
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* interface. All other chips have a max of 3 ports on
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* interface 0
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
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mask = 0xf; /* Set enables for 4 ports */
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else
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mask = 0x7; /* Set enables for 3 ports */
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/* Enable interface interrupts */
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csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
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csr.s.txpsh = mask;
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csr.s.txpop = mask;
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csr.s.ovrflw = mask;
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cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
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}
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/**
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* Enable GMX error reporting for the supplied interface
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*
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* @interface: Interface to enable
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*/
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void __cvmx_interrupt_gmxx_enable(int interface)
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{
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union cvmx_gmxx_inf_mode mode;
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union cvmx_gmxx_tx_int_en gmx_tx_int_en;
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int num_ports;
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int index;
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mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
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if (mode.s.en) {
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switch (mode.cn52xx.mode) {
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case 1: /* XAUI */
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num_ports = 1;
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break;
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case 2: /* SGMII */
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case 3: /* PICMG */
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num_ports = 4;
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break;
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default: /* Disabled */
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num_ports = 0;
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break;
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}
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} else
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num_ports = 0;
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} else {
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if (mode.s.en) {
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if (OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)) {
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/*
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* SPI on CN38XX and CN58XX report all
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* errors through port 0. RGMII needs
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* to check all 4 ports
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*/
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if (mode.s.type)
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num_ports = 1;
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else
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num_ports = 4;
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} else {
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/*
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* CN30XX, CN31XX, and CN50XX have two
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* or three ports. GMII and MII has 2,
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* RGMII has three
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*/
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if (mode.s.type)
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num_ports = 2;
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else
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num_ports = 3;
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}
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} else
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num_ports = 0;
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}
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gmx_tx_int_en.u64 = 0;
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if (num_ports) {
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if (OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX))
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gmx_tx_int_en.cn38xx.ncb_nxa = 1;
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gmx_tx_int_en.s.pko_nxa = 1;
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}
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gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
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cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
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for (index = 0; index < num_ports; index++)
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__cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
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}
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