232 lines
6.2 KiB
C
232 lines
6.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2017 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#ifndef __MIPS_ASM_MIPS_CPS_H__
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#define __MIPS_ASM_MIPS_CPS_H__
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/types.h>
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extern unsigned long __cps_access_bad_size(void)
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__compiletime_error("Bad size for CPS accessor");
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#define CPS_ACCESSOR_A(unit, off, name) \
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static inline void *addr_##unit##_##name(void) \
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{ \
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return mips_##unit##_base + (off); \
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}
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#define CPS_ACCESSOR_R(unit, sz, name) \
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static inline uint##sz##_t read_##unit##_##name(void) \
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{ \
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uint64_t val64; \
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\
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switch (sz) { \
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case 32: \
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return __raw_readl(addr_##unit##_##name()); \
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\
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case 64: \
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if (mips_cm_is64) \
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return __raw_readq(addr_##unit##_##name()); \
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\
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val64 = __raw_readl(addr_##unit##_##name() + 4); \
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val64 <<= 32; \
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val64 |= __raw_readl(addr_##unit##_##name()); \
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return val64; \
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\
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default: \
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return __cps_access_bad_size(); \
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} \
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}
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#define CPS_ACCESSOR_W(unit, sz, name) \
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static inline void write_##unit##_##name(uint##sz##_t val) \
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{ \
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switch (sz) { \
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case 32: \
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__raw_writel(val, addr_##unit##_##name()); \
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break; \
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\
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case 64: \
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if (mips_cm_is64) { \
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__raw_writeq(val, addr_##unit##_##name()); \
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break; \
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} \
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\
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__raw_writel((uint64_t)val >> 32, \
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addr_##unit##_##name() + 4); \
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__raw_writel(val, addr_##unit##_##name()); \
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break; \
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\
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default: \
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__cps_access_bad_size(); \
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break; \
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} \
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}
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#define CPS_ACCESSOR_M(unit, sz, name) \
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static inline void change_##unit##_##name(uint##sz##_t mask, \
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uint##sz##_t val) \
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{ \
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uint##sz##_t reg_val = read_##unit##_##name(); \
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reg_val &= ~mask; \
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reg_val |= val; \
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write_##unit##_##name(reg_val); \
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} \
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\
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static inline void set_##unit##_##name(uint##sz##_t val) \
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{ \
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change_##unit##_##name(val, val); \
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} \
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\
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static inline void clear_##unit##_##name(uint##sz##_t val) \
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{ \
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change_##unit##_##name(val, 0); \
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}
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#define CPS_ACCESSOR_RO(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_R(unit, sz, name)
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#define CPS_ACCESSOR_WO(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_W(unit, sz, name)
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#define CPS_ACCESSOR_RW(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_R(unit, sz, name) \
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CPS_ACCESSOR_W(unit, sz, name) \
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CPS_ACCESSOR_M(unit, sz, name)
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips-gic.h>
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/**
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* mips_cps_numclusters - return the number of clusters present in the system
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*
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* Returns the number of clusters in the system.
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*/
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static inline unsigned int mips_cps_numclusters(void)
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{
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if (mips_cm_revision() < CM_REV_CM3_5)
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return 1;
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return FIELD_GET(CM_GCR_CONFIG_NUM_CLUSTERS, read_gcr_config());
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}
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/**
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* mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
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* @cluster: the ID of the cluster whose config we want
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*
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* Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
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*
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* Returns the value of GCR_CONFIG.
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*/
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static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
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{
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uint64_t config;
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if (mips_cm_revision() < CM_REV_CM3_5) {
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/*
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* Prior to CM 3.5 we don't have the notion of multiple
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* clusters so we can trivially read the GCR_CONFIG register
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* within this cluster.
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*/
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WARN_ON(cluster != 0);
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config = read_gcr_config();
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} else {
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/*
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* From CM 3.5 onwards we read the CPC_CONFIG mirror of
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* GCR_CONFIG via the redirect region, since the CPC is always
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* powered up allowing us not to need to power up the CM.
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*/
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mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
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config = read_cpc_redir_config();
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mips_cm_unlock_other();
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}
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return config;
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}
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/**
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* mips_cps_numcores - return the number of cores present in a cluster
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* @cluster: the ID of the cluster whose core count we want
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*
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* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
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* zero if no Coherence Manager is present.
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*/
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static inline unsigned int mips_cps_numcores(unsigned int cluster)
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{
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if (!mips_cm_present())
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return 0;
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/* Add one before masking to handle 0xff indicating no cores */
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return FIELD_GET(CM_GCR_CONFIG_PCORES,
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mips_cps_cluster_config(cluster) + 1);
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}
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/**
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* mips_cps_numiocu - return the number of IOCUs present in a cluster
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* @cluster: the ID of the cluster whose IOCU count we want
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*
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* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
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* if no Coherence Manager is present.
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*/
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static inline unsigned int mips_cps_numiocu(unsigned int cluster)
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{
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if (!mips_cm_present())
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return 0;
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return FIELD_GET(CM_GCR_CONFIG_NUMIOCU,
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mips_cps_cluster_config(cluster));
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}
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/**
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* mips_cps_numvps - return the number of VPs (threads) supported by a core
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* @cluster: the ID of the cluster containing the core we want to examine
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* @core: the ID of the core whose VP count we want
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*
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* Returns the number of Virtual Processors (VPs, ie. hardware threads) that
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* are supported by the given @core in the given @cluster. If the core or the
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* kernel do not support hardware mutlti-threading this returns 1.
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*/
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static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
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{
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unsigned int cfg;
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if (!mips_cm_present())
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return 1;
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if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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&& (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
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return 1;
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mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
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if (mips_cm_revision() < CM_REV_CM3_5) {
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/*
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* Prior to CM 3.5 we can only have one cluster & don't have
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* CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
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*/
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cfg = read_gcr_co_config();
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} else {
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/*
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* From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
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* always powered, which allows us to not worry about powering
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* up the cluster's CM here.
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*/
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cfg = read_cpc_co_config();
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}
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mips_cm_unlock_other();
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return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1);
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}
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#endif /* __MIPS_ASM_MIPS_CPS_H__ */
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