306 lines
10 KiB
C
306 lines
10 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PGTABLE_32_H
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#define _ASM_PGTABLE_32_H
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <linux/linkage.h>
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#include <asm/cachectl.h>
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#include <asm/fixmap.h>
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#include <asm-generic/pgtable-nopmd.h>
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#ifdef CONFIG_HIGHMEM
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#include <asm/highmem.h>
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#endif
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/*
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* Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
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*
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* We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
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* our 2-level table layout would normally have a PGD entry cover a contiguous
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* 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
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* pointers, each pointing to a 4KB physical page). The problem is that 4MB,
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* spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
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* support, not one of the standard supported sizes (1MB,4MB,16MB,...).
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* To correct for this, when huge pages are enabled, we halve the number of
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* pointers a PTE page holds, making its last half go to waste. Correspondingly,
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* we double the number of PGD pages. Overall, page table memory overhead
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* increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
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*
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* NOTE: We don't yet support huge pages if extended-addressing is enabled
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* (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
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*/
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extern int temp_tlb_entry;
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/*
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* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
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* starting at the top and working down. This is for populating the
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* TLB before trap_init() puts the TLB miss handler in place. It
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* should be used only for entries matching the actual page tables,
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* to prevent inconsistencies.
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*/
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extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/*
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* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386. Some day
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* when we have proper page coloring support we can have a 1% quicker
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* tlb refill handling mechanism, but for now it is a bit slower but
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* works even with the cache aliasing problem the R4k and above have.
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*/
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
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# define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2 - 1)
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#else
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# define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2)
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use two-level, so
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* we don't really have any PUD/PMD directory physically.
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*/
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#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
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# define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
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#else
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# define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
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#endif
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#define PGD_TABLE_ORDER (__PGD_TABLE_ORDER >= 0 ? __PGD_TABLE_ORDER : 0)
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#define PUD_TABLE_ORDER aieeee_attempt_to_allocate_pud
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#define PMD_TABLE_ORDER aieeee_attempt_to_allocate_pmd
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#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
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#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
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# define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t) / 2)
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#else
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# define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
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#endif
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#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
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#define VMALLOC_START MAP_BASE
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#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
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#define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#endif
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
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#else
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#endif
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern void load_pgd(unsigned long pg_dir);
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extern pte_t invalid_pte_table[PTRS_PER_PTE];
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/*
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* Empty pgd/pmd entries point to the invalid_pte_table.
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*/
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == (unsigned long) invalid_pte_table;
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}
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static inline int pmd_bad(pmd_t pmd)
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{
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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/* pmd_huge(pmd) but inline */
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if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
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return 0;
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#endif
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if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
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return 1;
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return 0;
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}
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static inline int pmd_present(pmd_t pmd)
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{
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return pmd_val(pmd) != (unsigned long) invalid_pte_table;
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
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}
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#if defined(CONFIG_XPA)
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#define MAX_POSSIBLE_PHYSMEM_BITS 40
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#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
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static inline pte_t
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pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
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(pgprot_val(prot) & ~_PFNX_MASK);
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pte.pte_high = (pfn << _PFN_SHIFT) |
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(pgprot_val(prot) & ~_PFN_MASK);
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return pte;
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}
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#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#define MAX_POSSIBLE_PHYSMEM_BITS 36
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
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pte.pte_low = pgprot_val(prot);
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return pte;
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}
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#else
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#define MAX_POSSIBLE_PHYSMEM_BITS 32
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#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
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#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
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#define pfn_pmd(pfn, prot) __pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
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#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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/*
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
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* are !pte_none() && !pte_present().
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*/
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#if defined(CONFIG_CPU_R3K_TLB)
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/*
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* Format of swap PTEs:
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <----------- offset ------------> < type -> V G E 0 0 0 0 0 0 P
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*
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* E is the exclusive marker that is not stored in swap entries.
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* _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
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* unused.
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*/
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#define __swp_type(x) (((x).val >> 10) & 0x1f)
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#define __swp_offset(x) ((x).val >> 15)
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#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 10) | ((offset) << 15) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE (1 << 7)
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#else
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#if defined(CONFIG_XPA)
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/*
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* Format of swap PTEs:
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*
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* 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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* 0 0 0 0 0 0 E P <------------------ zeroes ------------------->
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <----------------- offset ------------------> < type -> V G 0 0
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*
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* E is the exclusive marker that is not stored in swap entries.
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* _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
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* unused.
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*/
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#define __swp_type(x) (((x).val >> 4) & 0x1f)
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#define __swp_offset(x) ((x).val >> 9)
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#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 4) | ((offset) << 9) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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/*
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* We borrow bit 57 (bit 25 in the low PTE) to store the exclusive marker in
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* swap PTEs.
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*/
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#define _PAGE_SWP_EXCLUSIVE (1 << 25)
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#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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/*
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* Format of swap PTEs:
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*
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* 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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* <------------------ zeroes -------------------> E P 0 0 0 0 0 0
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <------------------- offset --------------------> < type -> V G
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*
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* E is the exclusive marker that is not stored in swap entries.
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* _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
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* unused.
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*/
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#define __swp_type(x) (((x).val >> 2) & 0x1f)
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#define __swp_offset(x) ((x).val >> 7)
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#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 2) | ((offset) << 7) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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/*
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* We borrow bit 39 (bit 7 in the low PTE) to store the exclusive marker in swap
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* PTEs.
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*/
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#define _PAGE_SWP_EXCLUSIVE (1 << 7)
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#else
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/*
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* Format of swap PTEs:
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <------------- offset --------------> < type -> 0 0 0 0 0 0 E P
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*
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* E is the exclusive marker that is not stored in swap entries.
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* _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain
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* unused. The location of V and G varies.
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*/
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#define __swp_type(x) (((x).val >> 8) & 0x1f)
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#define __swp_offset(x) ((x).val >> 13)
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#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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/* We borrow bit 1 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE (1 << 1)
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#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
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#endif /* defined(CONFIG_CPU_R3K_TLB) */
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#endif /* _ASM_PGTABLE_32_H */
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