399 lines
13 KiB
C
399 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* asm-offsets.c: Calculate pt_regs and task_struct offsets.
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*
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* Copyright (C) 1996 David S. Miller
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* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*
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* Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#include <linux/compat.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/kbuild.h>
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#include <linux/suspend.h>
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#include <asm/cpu-info.h>
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#include <asm/pm.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/smp-cps.h>
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#include <linux/kvm_host.h>
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void output_ptreg_defines(void)
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{
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COMMENT("MIPS pt_regs offsets.");
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OFFSET(PT_R0, pt_regs, regs[0]);
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OFFSET(PT_R1, pt_regs, regs[1]);
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OFFSET(PT_R2, pt_regs, regs[2]);
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OFFSET(PT_R3, pt_regs, regs[3]);
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OFFSET(PT_R4, pt_regs, regs[4]);
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OFFSET(PT_R5, pt_regs, regs[5]);
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OFFSET(PT_R6, pt_regs, regs[6]);
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OFFSET(PT_R7, pt_regs, regs[7]);
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OFFSET(PT_R8, pt_regs, regs[8]);
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OFFSET(PT_R9, pt_regs, regs[9]);
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OFFSET(PT_R10, pt_regs, regs[10]);
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OFFSET(PT_R11, pt_regs, regs[11]);
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OFFSET(PT_R12, pt_regs, regs[12]);
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OFFSET(PT_R13, pt_regs, regs[13]);
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OFFSET(PT_R14, pt_regs, regs[14]);
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OFFSET(PT_R15, pt_regs, regs[15]);
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OFFSET(PT_R16, pt_regs, regs[16]);
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OFFSET(PT_R17, pt_regs, regs[17]);
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OFFSET(PT_R18, pt_regs, regs[18]);
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OFFSET(PT_R19, pt_regs, regs[19]);
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OFFSET(PT_R20, pt_regs, regs[20]);
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OFFSET(PT_R21, pt_regs, regs[21]);
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OFFSET(PT_R22, pt_regs, regs[22]);
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OFFSET(PT_R23, pt_regs, regs[23]);
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OFFSET(PT_R24, pt_regs, regs[24]);
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OFFSET(PT_R25, pt_regs, regs[25]);
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OFFSET(PT_R26, pt_regs, regs[26]);
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OFFSET(PT_R27, pt_regs, regs[27]);
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OFFSET(PT_R28, pt_regs, regs[28]);
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OFFSET(PT_R29, pt_regs, regs[29]);
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OFFSET(PT_R30, pt_regs, regs[30]);
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OFFSET(PT_R31, pt_regs, regs[31]);
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OFFSET(PT_LO, pt_regs, lo);
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OFFSET(PT_HI, pt_regs, hi);
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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OFFSET(PT_ACX, pt_regs, acx);
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#endif
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OFFSET(PT_EPC, pt_regs, cp0_epc);
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OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
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OFFSET(PT_STATUS, pt_regs, cp0_status);
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OFFSET(PT_CAUSE, pt_regs, cp0_cause);
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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OFFSET(PT_MPL, pt_regs, mpl);
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OFFSET(PT_MTP, pt_regs, mtp);
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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DEFINE(PT_SIZE, sizeof(struct pt_regs));
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BLANK();
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}
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void output_task_defines(void)
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{
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COMMENT("MIPS task_struct offsets.");
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OFFSET(TASK_THREAD_INFO, task_struct, stack);
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OFFSET(TASK_FLAGS, task_struct, flags);
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OFFSET(TASK_MM, task_struct, mm);
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OFFSET(TASK_PID, task_struct, pid);
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#if defined(CONFIG_STACKPROTECTOR)
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OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
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#endif
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DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
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BLANK();
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}
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void output_thread_info_defines(void)
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{
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COMMENT("MIPS thread_info offsets.");
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OFFSET(TI_TASK, thread_info, task);
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OFFSET(TI_FLAGS, thread_info, flags);
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OFFSET(TI_TP_VALUE, thread_info, tp_value);
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OFFSET(TI_CPU, thread_info, cpu);
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OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
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OFFSET(TI_REGS, thread_info, regs);
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DEFINE(_THREAD_SIZE, THREAD_SIZE);
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DEFINE(_THREAD_MASK, THREAD_MASK);
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DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
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DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
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BLANK();
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}
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void output_thread_defines(void)
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{
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COMMENT("MIPS specific thread_struct offsets.");
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OFFSET(THREAD_REG16, task_struct, thread.reg16);
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OFFSET(THREAD_REG17, task_struct, thread.reg17);
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OFFSET(THREAD_REG18, task_struct, thread.reg18);
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OFFSET(THREAD_REG19, task_struct, thread.reg19);
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OFFSET(THREAD_REG20, task_struct, thread.reg20);
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OFFSET(THREAD_REG21, task_struct, thread.reg21);
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OFFSET(THREAD_REG22, task_struct, thread.reg22);
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OFFSET(THREAD_REG23, task_struct, thread.reg23);
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OFFSET(THREAD_REG29, task_struct, thread.reg29);
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OFFSET(THREAD_REG30, task_struct, thread.reg30);
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OFFSET(THREAD_REG31, task_struct, thread.reg31);
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OFFSET(THREAD_STATUS, task_struct,
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thread.cp0_status);
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OFFSET(THREAD_BVADDR, task_struct, \
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thread.cp0_badvaddr);
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OFFSET(THREAD_BUADDR, task_struct, \
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thread.cp0_baduaddr);
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OFFSET(THREAD_ECODE, task_struct, \
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thread.error_code);
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OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
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BLANK();
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}
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#ifdef CONFIG_MIPS_FP_SUPPORT
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void output_thread_fpu_defines(void)
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{
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OFFSET(THREAD_FPU, task_struct, thread.fpu);
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OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
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OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
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OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
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OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
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OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
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OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
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OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
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OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
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OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
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OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
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OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
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OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
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OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
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OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
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OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
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OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
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OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
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OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
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OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
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OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
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OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
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OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
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OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
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OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
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OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
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OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
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OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
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OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
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OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
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OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
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OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
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OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
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OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
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OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
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BLANK();
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}
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#endif
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void output_mm_defines(void)
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{
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COMMENT("Size of struct page");
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DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
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BLANK();
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COMMENT("Linux mm_struct offsets.");
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OFFSET(MM_USERS, mm_struct, mm_users);
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OFFSET(MM_PGD, mm_struct, pgd);
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OFFSET(MM_CONTEXT, mm_struct, context);
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BLANK();
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DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
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DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
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DEFINE(_PTE_T_SIZE, sizeof(pte_t));
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BLANK();
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DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
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#ifndef __PAGETABLE_PMD_FOLDED
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DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
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#endif
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DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
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BLANK();
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BLANK();
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DEFINE(_PMD_SHIFT, PMD_SHIFT);
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DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
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BLANK();
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DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
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DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
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DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
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BLANK();
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DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
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DEFINE(_PAGE_SIZE, PAGE_SIZE);
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BLANK();
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}
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#ifdef CONFIG_32BIT
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void output_sc_defines(void)
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{
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COMMENT("Linux sigcontext offsets.");
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OFFSET(SC_REGS, sigcontext, sc_regs);
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OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
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OFFSET(SC_ACX, sigcontext, sc_acx);
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OFFSET(SC_MDHI, sigcontext, sc_mdhi);
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OFFSET(SC_MDLO, sigcontext, sc_mdlo);
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OFFSET(SC_PC, sigcontext, sc_pc);
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OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
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OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
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OFFSET(SC_HI1, sigcontext, sc_hi1);
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OFFSET(SC_LO1, sigcontext, sc_lo1);
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OFFSET(SC_HI2, sigcontext, sc_hi2);
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OFFSET(SC_LO2, sigcontext, sc_lo2);
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OFFSET(SC_HI3, sigcontext, sc_hi3);
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OFFSET(SC_LO3, sigcontext, sc_lo3);
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BLANK();
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}
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#endif
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#ifdef CONFIG_64BIT
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void output_sc_defines(void)
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{
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COMMENT("Linux sigcontext offsets.");
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OFFSET(SC_REGS, sigcontext, sc_regs);
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OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
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OFFSET(SC_MDHI, sigcontext, sc_mdhi);
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OFFSET(SC_MDLO, sigcontext, sc_mdlo);
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OFFSET(SC_PC, sigcontext, sc_pc);
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OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
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BLANK();
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}
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#endif
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void output_signal_defined(void)
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{
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COMMENT("Linux signal numbers.");
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DEFINE(_SIGHUP, SIGHUP);
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DEFINE(_SIGINT, SIGINT);
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DEFINE(_SIGQUIT, SIGQUIT);
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DEFINE(_SIGILL, SIGILL);
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DEFINE(_SIGTRAP, SIGTRAP);
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DEFINE(_SIGIOT, SIGIOT);
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DEFINE(_SIGABRT, SIGABRT);
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DEFINE(_SIGEMT, SIGEMT);
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DEFINE(_SIGFPE, SIGFPE);
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DEFINE(_SIGKILL, SIGKILL);
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DEFINE(_SIGBUS, SIGBUS);
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DEFINE(_SIGSEGV, SIGSEGV);
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DEFINE(_SIGSYS, SIGSYS);
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DEFINE(_SIGPIPE, SIGPIPE);
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DEFINE(_SIGALRM, SIGALRM);
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DEFINE(_SIGTERM, SIGTERM);
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DEFINE(_SIGUSR1, SIGUSR1);
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DEFINE(_SIGUSR2, SIGUSR2);
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DEFINE(_SIGCHLD, SIGCHLD);
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DEFINE(_SIGPWR, SIGPWR);
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DEFINE(_SIGWINCH, SIGWINCH);
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DEFINE(_SIGURG, SIGURG);
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DEFINE(_SIGIO, SIGIO);
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DEFINE(_SIGSTOP, SIGSTOP);
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DEFINE(_SIGTSTP, SIGTSTP);
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DEFINE(_SIGCONT, SIGCONT);
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DEFINE(_SIGTTIN, SIGTTIN);
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DEFINE(_SIGTTOU, SIGTTOU);
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DEFINE(_SIGVTALRM, SIGVTALRM);
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DEFINE(_SIGPROF, SIGPROF);
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DEFINE(_SIGXCPU, SIGXCPU);
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DEFINE(_SIGXFSZ, SIGXFSZ);
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BLANK();
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}
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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void output_octeon_cop2_state_defines(void)
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{
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COMMENT("Octeon specific octeon_cop2_state offsets.");
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OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
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OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
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OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
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OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
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OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
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OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
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OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
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OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
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OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
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OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
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OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
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OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
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OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
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OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
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OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
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OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
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OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
|
||
|
|
OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
|
||
|
|
OFFSET(THREAD_CP2, task_struct, thread.cp2);
|
||
|
|
OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
|
||
|
|
BLANK();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_HIBERNATION
|
||
|
|
void output_pbe_defines(void)
|
||
|
|
{
|
||
|
|
COMMENT(" Linux struct pbe offsets. ");
|
||
|
|
OFFSET(PBE_ADDRESS, pbe, address);
|
||
|
|
OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
|
||
|
|
OFFSET(PBE_NEXT, pbe, next);
|
||
|
|
DEFINE(PBE_SIZE, sizeof(struct pbe));
|
||
|
|
BLANK();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_CPU_PM
|
||
|
|
void output_pm_defines(void)
|
||
|
|
{
|
||
|
|
COMMENT(" PM offsets. ");
|
||
|
|
#ifdef CONFIG_EVA
|
||
|
|
OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
|
||
|
|
OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
|
||
|
|
OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
|
||
|
|
#endif
|
||
|
|
OFFSET(SSS_SP, mips_static_suspend_state, sp);
|
||
|
|
BLANK();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_MIPS_FP_SUPPORT
|
||
|
|
void output_kvm_defines(void)
|
||
|
|
{
|
||
|
|
COMMENT(" KVM/MIPS Specific offsets. ");
|
||
|
|
|
||
|
|
OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
|
||
|
|
OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
|
||
|
|
OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
|
||
|
|
OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
|
||
|
|
OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
|
||
|
|
OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
|
||
|
|
OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
|
||
|
|
OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
|
||
|
|
OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
|
||
|
|
OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
|
||
|
|
OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
|
||
|
|
OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
|
||
|
|
OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
|
||
|
|
OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
|
||
|
|
OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
|
||
|
|
OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
|
||
|
|
OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
|
||
|
|
OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
|
||
|
|
OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
|
||
|
|
OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
|
||
|
|
OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
|
||
|
|
OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
|
||
|
|
OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
|
||
|
|
OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
|
||
|
|
OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
|
||
|
|
OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
|
||
|
|
OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
|
||
|
|
OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
|
||
|
|
OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
|
||
|
|
OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
|
||
|
|
OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
|
||
|
|
OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
|
||
|
|
|
||
|
|
OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
|
||
|
|
OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
|
||
|
|
BLANK();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_MIPS_CPS
|
||
|
|
void output_cps_defines(void)
|
||
|
|
{
|
||
|
|
COMMENT(" MIPS CPS offsets. ");
|
||
|
|
|
||
|
|
OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
|
||
|
|
OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
|
||
|
|
DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
|
||
|
|
|
||
|
|
OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
|
||
|
|
OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
|
||
|
|
OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
|
||
|
|
DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
|
||
|
|
}
|
||
|
|
#endif
|