349 lines
10 KiB
C
349 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/kernel_stat.h>
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#include <asm/errno.h>
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#include <asm/irq_regs.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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#include <asm/sibyte/bcm1480_scd.h>
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#include <asm/sibyte/sb1250_uart.h>
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#include <asm/sibyte/sb1250.h>
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/*
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* These are the routines that handle all the low level interrupt stuff.
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* Actions handled here are: initialization of the interrupt map, requesting of
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* interrupt lines by handlers, dispatching if interrupts to handlers, probing
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* for interrupt lines
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*/
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#ifdef CONFIG_PCI
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extern unsigned long ht_eoi_space;
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#endif
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/* Store the CPU id (not the logical number) */
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int bcm1480_irq_owner[BCM1480_NR_IRQS];
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static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock);
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void bcm1480_mask_irq(int cpu, int irq)
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{
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unsigned long flags, hl_spacing;
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u64 cur_ints;
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raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
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hl_spacing = 0;
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if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
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hl_spacing = BCM1480_IMR_HL_SPACING;
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irq -= BCM1480_NR_IRQS_HALF;
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}
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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cur_ints |= (((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
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}
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void bcm1480_unmask_irq(int cpu, int irq)
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{
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unsigned long flags, hl_spacing;
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u64 cur_ints;
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raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
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hl_spacing = 0;
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if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
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hl_spacing = BCM1480_IMR_HL_SPACING;
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irq -= BCM1480_NR_IRQS_HALF;
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}
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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cur_ints &= ~(((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
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}
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#ifdef CONFIG_SMP
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static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask,
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bool force)
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{
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unsigned int irq_dirty, irq = d->irq;
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int i = 0, old_cpu, cpu, int_on, k;
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u64 cur_ints;
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unsigned long flags;
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i = cpumask_first_and(mask, cpu_online_mask);
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/* Convert logical CPU to physical CPU */
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cpu = cpu_logical_map(i);
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/* Protect against other affinity changers and IMR manipulation */
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raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
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/* Swizzle each CPU's IMR (but leave the IP selection alone) */
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old_cpu = bcm1480_irq_owner[irq];
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irq_dirty = irq;
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if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
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irq_dirty -= BCM1480_NR_IRQS_HALF;
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}
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for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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int_on = !(cur_ints & (((u64) 1) << irq_dirty));
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if (int_on) {
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/* If it was on, mask it */
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cur_ints |= (((u64) 1) << irq_dirty);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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}
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bcm1480_irq_owner[irq] = cpu;
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if (int_on) {
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/* unmask for the new CPU */
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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cur_ints &= ~(((u64) 1) << irq_dirty);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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}
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}
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raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
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return 0;
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}
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#endif
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/*****************************************************************************/
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static void disable_bcm1480_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
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}
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static void enable_bcm1480_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
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}
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static void ack_bcm1480_irq(struct irq_data *d)
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{
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unsigned int irq_dirty, irq = d->irq;
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u64 pending;
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int k;
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/*
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* If the interrupt was an HT interrupt, now is the time to
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* clear it. NOTE: we assume the HT bridge was set up to
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* deliver the interrupts to all CPUs (which makes affinity
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* changing easier for us)
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*/
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irq_dirty = irq;
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if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
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irq_dirty -= BCM1480_NR_IRQS_HALF;
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}
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for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
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pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
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R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
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pending &= ((u64)1 << (irq_dirty));
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if (pending) {
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#ifdef CONFIG_SMP
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int i;
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for (i=0; i<NR_CPUS; i++) {
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/*
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* Clear for all CPUs so an affinity switch
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* doesn't find an old status
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*/
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__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
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R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
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}
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#else
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__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
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#endif
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/*
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* Generate EOI. For Pass 1 parts, EOI is a nop. For
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* Pass 2, the LDT world may be edge-triggered, but
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* this EOI shouldn't hurt. If they are
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* level-sensitive, the EOI is required.
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*/
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#ifdef CONFIG_PCI
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if (ht_eoi_space)
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*(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
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#endif
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}
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}
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bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
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}
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static struct irq_chip bcm1480_irq_type = {
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.name = "BCM1480-IMR",
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.irq_mask_ack = ack_bcm1480_irq,
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.irq_mask = disable_bcm1480_irq,
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.irq_unmask = enable_bcm1480_irq,
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#ifdef CONFIG_SMP
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.irq_set_affinity = bcm1480_set_affinity
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#endif
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};
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void __init init_bcm1480_irqs(void)
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{
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int i;
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for (i = 0; i < BCM1480_NR_IRQS; i++) {
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irq_set_chip_and_handler(i, &bcm1480_irq_type,
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handle_level_irq);
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bcm1480_irq_owner[i] = 0;
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}
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}
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/*
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* init_IRQ is called early in the boot sequence from init/main.c. It
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* is responsible for setting up the interrupt mapper and installing the
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* handler that will be responsible for dispatching interrupts to the
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* "right" place.
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*/
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/*
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* For now, map all interrupts to IP[2]. We could save
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* some cycles by parceling out system interrupts to different
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* IP lines, but keep it simple for bringup. We'll also direct
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* all interrupts to a single CPU; we should probably route
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* PCI and LDT to one cpu and everything else to the other
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* to balance the load a bit.
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*
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* On the second cpu, everything is set to IP5, which is
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* ignored, EXCEPT the mailbox interrupt. That one is
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* set to IP[2] so it is handled. This is needed so we
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* can do cross-cpu function calls, as required by SMP
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*/
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#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
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#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
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#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
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#define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
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#define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
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void __init arch_init_irq(void)
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{
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unsigned int i, cpu;
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u64 tmp;
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unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
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STATUSF_IP1 | STATUSF_IP0;
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/* Default everything to IP2 */
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/* Start with _high registers which has no bit 0 interrupt source */
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for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(IMR_IP2_VAL,
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IOADDR(A_BCM1480_IMR_REGISTER(cpu,
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R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
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}
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}
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/* Now do _low registers */
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for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(IMR_IP2_VAL,
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IOADDR(A_BCM1480_IMR_REGISTER(cpu,
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R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
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}
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}
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init_bcm1480_irqs();
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/*
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* Map the high 16 bits of mailbox_0 registers to IP[3], for
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* inter-cpu messages
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*/
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/* Was I1 */
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
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(K_BCM1480_INT_MBOX_0_0 << 3)));
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}
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/* Clear the mailboxes. The firmware may leave them dirty */
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(0xffffffffffffffffULL,
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IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
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__raw_writeq(0xffffffffffffffffULL,
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IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
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}
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/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
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tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
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}
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tmp = ~((u64) 0);
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for (cpu = 0; cpu < 4; cpu++) {
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__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
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}
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/*
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* Note that the timer interrupts are also mapped, but this is
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* done in bcm1480_time_init(). Also, the profiling driver
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* does its own management of IP7.
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*/
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/* Enable necessary IPs, disable the rest */
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change_c0_status(ST0_IM, imask);
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}
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extern void bcm1480_mailbox_interrupt(void);
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static inline void dispatch_ip2(void)
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{
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unsigned long long mask_h, mask_l;
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unsigned int cpu = smp_processor_id();
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unsigned long base;
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/*
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* Default...we've hit an IP[2] interrupt, which means we've got to
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* check the 1480 interrupt registers to figure out what to do. Need
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* to detect which CPU we're on, now that smp_affinity is supported.
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*/
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base = A_BCM1480_IMR_MAPPER(cpu);
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mask_h = __raw_readq(
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IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
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mask_l = __raw_readq(
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IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
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if (mask_h) {
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if (mask_h ^ 1)
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|
do_IRQ(fls64(mask_h) - 1);
|
||
|
|
else if (mask_l)
|
||
|
|
do_IRQ(63 + fls64(mask_l));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
asmlinkage void plat_irq_dispatch(void)
|
||
|
|
{
|
||
|
|
unsigned int cpu = smp_processor_id();
|
||
|
|
unsigned int pending;
|
||
|
|
|
||
|
|
pending = read_c0_cause() & read_c0_status();
|
||
|
|
|
||
|
|
if (pending & CAUSEF_IP4)
|
||
|
|
do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
|
||
|
|
#ifdef CONFIG_SMP
|
||
|
|
else if (pending & CAUSEF_IP3)
|
||
|
|
bcm1480_mailbox_interrupt();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
else if (pending & CAUSEF_IP2)
|
||
|
|
dispatch_ip2();
|
||
|
|
}
|