297 lines
10 KiB
C
297 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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#define H_PTE_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 64KB = 16MB
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#define H_PMD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16MB = 16GB
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#define H_PUD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16GB = 16TB
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#define H_PGD_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 16TB = 4PB
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/*
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* If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
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* if we increase SECTIONS_WIDTH we will not store node details in page->flags and
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* page_to_nid does a page->section->node lookup
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* Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
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* memory requirements with large number of sections.
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* 51 bits is the max physical real address on POWER9
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*/
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#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME)
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#define H_MAX_PHYSMEM_BITS 51
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#else
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#define H_MAX_PHYSMEM_BITS 46
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#endif
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/*
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* Each context is 512TB size. SLB miss for first context/default context
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* is handled in the hotpath.
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*/
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#define MAX_EA_BITS_PER_CONTEXT 49
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#define REGION_SHIFT MAX_EA_BITS_PER_CONTEXT
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/*
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* We use one context for each MAP area.
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*/
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#define H_KERN_MAP_SIZE (1UL << MAX_EA_BITS_PER_CONTEXT)
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/*
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* Define the address range of the kernel non-linear virtual area
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* 2PB
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*/
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#define H_KERN_VIRT_START ASM_CONST(0xc008000000000000)
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/*
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* 64k aligned address free up few of the lower bits of RPN for us
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* We steal that here. For more deatils look at pte_pfn/pfn_pte()
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*/
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#define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */
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#define H_PAGE_4K_PFN _RPAGE_RPN1 /* PFN is for a single 4k page */
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#define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
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#define H_PAGE_HASHPTE _RPAGE_RPN43 /* PTE has associated HPTE */
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/* memory key bits. */
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#define H_PTE_PKEY_BIT4 _RPAGE_PKEY_BIT4
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#define H_PTE_PKEY_BIT3 _RPAGE_PKEY_BIT3
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#define H_PTE_PKEY_BIT2 _RPAGE_PKEY_BIT2
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#define H_PTE_PKEY_BIT1 _RPAGE_PKEY_BIT1
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#define H_PTE_PKEY_BIT0 _RPAGE_PKEY_BIT0
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/*
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* We need to differentiate between explicit huge page and THP huge
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* page, since THP huge page also need to track real subpage details
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*/
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#define H_PAGE_THP_HUGE H_PAGE_4K_PFN
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO)
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/*
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* We use a 2K PTE page fragment and another 2K for storing
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* real_pte_t hash index
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* 8 bytes per each pte entry and another 8 bytes for storing
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* slot details.
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*/
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#define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3 + 1)
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#define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
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#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
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#define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3 + 1)
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#else
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#define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3)
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#endif
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#define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
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#ifndef __ASSEMBLY__
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#include <asm/errno.h>
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/*
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* With 64K pages on hash table, we have a special PTE format that
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* uses a second "half" of the page table to encode sub-page information
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* in order to deal with 64K made of 4K HW pages. Thus we override the
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* generic accessors and iterators here
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*/
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#define __real_pte __real_pte
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static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
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{
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real_pte_t rpte;
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unsigned long *hidxp;
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rpte.pte = pte;
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/*
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* Ensure that we do not read the hidx before we read the PTE. Because
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* the writer side is expected to finish writing the hidx first followed
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* by the PTE, by using smp_wmb(). pte_set_hash_slot() ensures that.
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*/
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smp_rmb();
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hidxp = (unsigned long *)(ptep + offset);
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rpte.hidx = *hidxp;
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return rpte;
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}
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/*
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* shift the hidx representation by one-modulo-0xf; i.e hidx 0 is respresented
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* as 1, 1 as 2,... , and 0xf as 0. This convention lets us represent a
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* invalid hidx 0xf with a 0x0 bit value. PTEs are anyway zero'd when
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* allocated. We dont have to zero them gain; thus save on the initialization.
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*/
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#define HIDX_UNSHIFT_BY_ONE(x) ((x + 0xfUL) & 0xfUL) /* shift backward by one */
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#define HIDX_SHIFT_BY_ONE(x) ((x + 0x1UL) & 0xfUL) /* shift forward by one */
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#define HIDX_BITS(x, index) (x << (index << 2))
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#define BITS_TO_HIDX(x, index) ((x >> (index << 2)) & 0xfUL)
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#define INVALID_RPTE_HIDX 0x0UL
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static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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{
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return HIDX_UNSHIFT_BY_ONE(BITS_TO_HIDX(rpte.hidx, index));
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}
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/*
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* Commit the hidx and return PTE bits that needs to be modified. The caller is
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* expected to modify the PTE bits accordingly and commit the PTE to memory.
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*/
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static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
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unsigned int subpg_index,
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unsigned long hidx, int offset)
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{
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unsigned long *hidxp = (unsigned long *)(ptep + offset);
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rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index);
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*hidxp = rpte.hidx | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index);
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/*
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* Anyone reading PTE must ensure hidx bits are read after reading the
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* PTE by using the read-side barrier smp_rmb(). __real_pte() can be
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* used for that.
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*/
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smp_wmb();
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/* No PTE bits to be modified, return 0x0UL */
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return 0x0UL;
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}
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#define __rpte_to_pte(r) ((r).pte)
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extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);
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/*
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* Trick: we set __end to va + 64k, which happens works for
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* a 16M page as well as we want only one iteration
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*/
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#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
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do { \
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unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \
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unsigned __split = (psize == MMU_PAGE_4K || \
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psize == MMU_PAGE_64K_AP); \
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shift = mmu_psize_defs[psize].shift; \
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for (index = 0; vpn < __end; index++, \
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vpn += (1L << (shift - VPN_SHIFT))) { \
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if (!__split || __rpte_sub_valid(rpte, index))
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#define pte_iterate_hashed_end() } } while(0)
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#define pte_pagesize_index(mm, addr, pte) \
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(((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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extern int remap_pfn_range(struct vm_area_struct *, unsigned long addr,
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unsigned long pfn, unsigned long size, pgprot_t);
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static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long addr,
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unsigned long pfn, pgprot_t prot)
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{
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if (pfn > (PTE_RPN_MASK >> PAGE_SHIFT)) {
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WARN(1, "remap_4k_pfn called with wrong pfn value\n");
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return -EINVAL;
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}
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return remap_pfn_range(vma, addr, pfn, PAGE_SIZE,
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__pgprot(pgprot_val(prot) | H_PAGE_4K_PFN));
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}
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#define H_PTE_TABLE_SIZE PTE_FRAG_SIZE
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#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE)
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#define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \
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(sizeof(unsigned long) << PMD_INDEX_SIZE))
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#else
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#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#endif
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#ifdef CONFIG_HUGETLB_PAGE
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#define H_PUD_TABLE_SIZE ((sizeof(pud_t) << PUD_INDEX_SIZE) + \
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(sizeof(unsigned long) << PUD_INDEX_SIZE))
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#else
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#define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
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#endif
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#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static inline char *get_hpte_slot_array(pmd_t *pmdp)
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{
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/*
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* The hpte hindex is stored in the pgtable whose address is in the
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* second half of the PMD
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*
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* Order this load with the test for pmd_trans_huge in the caller
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*/
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smp_rmb();
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return *(char **)(pmdp + PTRS_PER_PMD);
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}
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/*
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* The linux hugepage PMD now include the pmd entries followed by the address
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* to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
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* [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per
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* each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
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* with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
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*
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* The top three bits are intentionally left as zero. This memory location
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* are also used as normal page PTE pointers. So if we have any pointers
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* left around while we collapse a hugepage, we need to make sure
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* _PAGE_PRESENT bit of that is zero when we look at them
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*/
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static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
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{
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return hpte_slot_array[index] & 0x1;
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}
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static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
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int index)
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{
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return hpte_slot_array[index] >> 1;
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}
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static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
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unsigned int index, unsigned int hidx)
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{
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hpte_slot_array[index] = (hidx << 1) | 0x1;
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}
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/*
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*
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* For core kernel code by design pmd_trans_huge is never run on any hugetlbfs
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* page. The hugetlbfs page table walking and mangling paths are totally
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* separated form the core VM paths and they're differentiated by
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* VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run.
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*
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* pmd_trans_huge() is defined as false at build time if
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* CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build
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* time in such case.
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*
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* For ppc64 we need to differntiate from explicit hugepages from THP, because
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* for THP we also track the subpage details at the pmd level. We don't do
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* that for explicit huge pages.
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*
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*/
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static inline int hash__pmd_trans_huge(pmd_t pmd)
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{
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return !!((pmd_val(pmd) & (_PAGE_PTE | H_PAGE_THP_HUGE | _PAGE_DEVMAP)) ==
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(_PAGE_PTE | H_PAGE_THP_HUGE));
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}
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static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
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{
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return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
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}
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static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
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}
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extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp,
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unsigned long clr, unsigned long set);
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extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable);
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extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
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extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp);
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extern int hash__has_transparent_hugepage(void);
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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static inline pmd_t hash__pmd_mkdevmap(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE | _PAGE_DEVMAP));
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */
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