299 lines
7.9 KiB
C
299 lines
7.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Port for PPC64 David Engebretsen, IBM Corp.
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <linux/syscalls.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
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#include <linux/of.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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/* pci_io_base -- the base address from which io bars are offsets.
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* This is the lowest I/O base address (so bar values are always positive),
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* and it *must* be the start of ISA space if an ISA bus exists because
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* ISA drivers use hard coded offsets. If no ISA bus exists nothing
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* is mapped on the first 64K of IO space
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*/
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unsigned long pci_io_base;
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EXPORT_SYMBOL(pci_io_base);
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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printk(KERN_INFO "PCI: Probing PCI hardware\n");
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/* For now, override phys_mem_access_prot. If we need it,g
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* later, we may move that initialization to each ppc_md
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*/
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ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
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/* On ppc64, we always enable PCI domains and we keep domain 0
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* backward compatible in /proc for video cards
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*/
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pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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pcibios_scan_phb(hose);
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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/* Add devices. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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pci_bus_add_devices(hose->bus);
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/* Call machine dependent fixup */
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if (ppc_md.pcibios_fixup)
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ppc_md.pcibios_fixup();
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printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
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return 0;
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}
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subsys_initcall(pcibios_init);
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int pcibios_unmap_io_space(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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WARN_ON(bus == NULL);
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/* If this is not a PHB, we only flush the hash table over
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* the area mapped by this bridge. We don't play with the PTE
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* mappings since we might have to deal with sub-page alignments
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* so flushing the hash table is the only sane way to make sure
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* that no hash entries are covering that removed bridge area
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* while still allowing other busses overlapping those pages
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*
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* Note: If we ever support P2P hotplug on Book3E, we'll have
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* to do an appropriate TLB flush here too
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*/
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if (bus->self) {
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#ifdef CONFIG_PPC_BOOK3S_64
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struct resource *res = bus->resource[0];
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#endif
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pr_debug("IO unmapping for PCI-PCI bridge %s\n",
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pci_name(bus->self));
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#ifdef CONFIG_PPC_BOOK3S_64
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__flush_hash_table_range(res->start + _IO_BASE,
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res->end + _IO_BASE + 1);
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#endif
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return 0;
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}
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/* Get the host bridge */
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hose = pci_bus_to_host(bus);
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pr_debug("IO unmapping for PHB %pOF\n", hose->dn);
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pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
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iounmap(hose->io_base_alloc);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
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void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size)
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{
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struct vm_struct *area;
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unsigned long addr;
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WARN_ON_ONCE(paddr & ~PAGE_MASK);
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WARN_ON_ONCE(size & ~PAGE_MASK);
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/*
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* Let's allocate some IO space for that guy. We don't pass VM_IOREMAP
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* because we don't care about alignment tricks that the core does in
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* that case. Maybe we should due to stupid card with incomplete
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* address decoding but I'd rather not deal with those outside of the
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* reserved 64K legacy region.
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*/
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area = __get_vm_area_caller(size, VM_IOREMAP, PHB_IO_BASE, PHB_IO_END,
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__builtin_return_address(0));
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if (!area)
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return NULL;
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addr = (unsigned long)area->addr;
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if (ioremap_page_range(addr, addr + size, paddr,
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pgprot_noncached(PAGE_KERNEL))) {
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vunmap_range(addr, addr + size);
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return NULL;
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}
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return (void __iomem *)addr;
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}
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EXPORT_SYMBOL_GPL(ioremap_phb);
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static int pcibios_map_phb_io_space(struct pci_controller *hose)
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{
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unsigned long phys_page;
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unsigned long size_page;
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unsigned long io_virt_offset;
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phys_page = ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
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size_page = ALIGN(hose->pci_io_size, PAGE_SIZE);
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/* Make sure IO area address is clear */
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hose->io_base_alloc = NULL;
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/* If there's no IO to map on that bus, get away too */
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if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
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return 0;
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/* Let's allocate some IO space for that guy. We don't pass
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* VM_IOREMAP because we don't care about alignment tricks that
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* the core does in that case. Maybe we should due to stupid card
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* with incomplete address decoding but I'd rather not deal with
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* those outside of the reserved 64K legacy region.
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*/
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hose->io_base_alloc = ioremap_phb(phys_page, size_page);
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if (!hose->io_base_alloc)
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return -ENOMEM;
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hose->io_base_virt = hose->io_base_alloc +
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hose->io_base_phys - phys_page;
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pr_debug("IO mapping for PHB %pOF\n", hose->dn);
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pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
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hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
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pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
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hose->pci_io_size, size_page);
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/* Fixup hose IO resource */
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io_virt_offset = pcibios_io_space_offset(hose);
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hose->io_resource.start += io_virt_offset;
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hose->io_resource.end += io_virt_offset;
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pr_debug(" hose->io_resource=%pR\n", &hose->io_resource);
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return 0;
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}
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int pcibios_map_io_space(struct pci_bus *bus)
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{
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WARN_ON(bus == NULL);
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/* If this not a PHB, nothing to do, page tables still exist and
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* thus HPTEs will be faulted in when needed
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*/
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if (bus->self) {
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pr_debug("IO mapping for PCI-PCI bridge %s\n",
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pci_name(bus->self));
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pr_debug(" virt=0x%016llx...0x%016llx\n",
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bus->resource[0]->start + _IO_BASE,
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bus->resource[0]->end + _IO_BASE);
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return 0;
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}
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return pcibios_map_phb_io_space(pci_bus_to_host(bus));
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}
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EXPORT_SYMBOL_GPL(pcibios_map_io_space);
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void pcibios_setup_phb_io_space(struct pci_controller *hose)
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{
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pcibios_map_phb_io_space(hose);
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}
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#define IOBASE_BRIDGE_NUMBER 0
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#define IOBASE_MEMORY 1
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#define IOBASE_IO 2
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#define IOBASE_ISA_IO 3
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#define IOBASE_ISA_MEM 4
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SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus,
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unsigned long, in_devfn)
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{
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struct pci_controller* hose;
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struct pci_bus *tmp_bus, *bus = NULL;
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struct device_node *hose_node;
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/* Argh ! Please forgive me for that hack, but that's the
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* simplest way to get existing XFree to not lockup on some
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* G5 machines... So when something asks for bus 0 io base
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* (bus 0 is HT root), we return the AGP one instead.
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*/
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if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
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struct device_node *agp;
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agp = of_find_compatible_node(NULL, NULL, "u3-agp");
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if (agp)
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in_bus = 0xf0;
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of_node_put(agp);
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}
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/* That syscall isn't quite compatible with PCI domains, but it's
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* used on pre-domains setup. We return the first match
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*/
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list_for_each_entry(tmp_bus, &pci_root_buses, node) {
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if (in_bus >= tmp_bus->number &&
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in_bus <= tmp_bus->busn_res.end) {
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bus = tmp_bus;
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break;
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}
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}
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if (bus == NULL || bus->dev.of_node == NULL)
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return -ENODEV;
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hose_node = bus->dev.of_node;
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hose = PCI_DN(hose_node)->phb;
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switch (which) {
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case IOBASE_BRIDGE_NUMBER:
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return (long)hose->first_busno;
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case IOBASE_MEMORY:
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return (long)hose->mem_offset[0];
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case IOBASE_IO:
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return (long)hose->io_base_phys;
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case IOBASE_ISA_IO:
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return (long)isa_io_base;
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case IOBASE_ISA_MEM:
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return -EINVAL;
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}
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return -EOPNOTSUPP;
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}
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#ifdef CONFIG_NUMA
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int pcibus_to_node(struct pci_bus *bus)
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{
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struct pci_controller *phb = pci_bus_to_host(bus);
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return phb->node;
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}
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EXPORT_SYMBOL(pcibus_to_node);
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#endif
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#ifdef CONFIG_PPC_PMAC
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int pci_device_from_OF_node(struct device_node *np, u8 *bus, u8 *devfn)
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{
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if (!PCI_DN(np))
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return -ENODEV;
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*bus = PCI_DN(np)->busno;
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*devfn = PCI_DN(np)->devfn;
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return 0;
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}
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#endif
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