100 lines
1.9 KiB
ArmAsm
100 lines
1.9 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* vDSO provided cache flush routines
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*
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* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
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* IBM Corp.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/vdso.h>
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#include <asm/vdso_datapage.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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.text
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/*
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* Default "generic" version of __kernel_sync_dicache.
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*
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* void __kernel_sync_dicache(unsigned long start, unsigned long end)
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*
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* Flushes the data cache & invalidate the instruction cache for the
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* provided range [start, end[
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*/
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V_FUNCTION_BEGIN(__kernel_sync_dicache)
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.cfi_startproc
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BEGIN_FTR_SECTION
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b 3f
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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#ifdef CONFIG_PPC64
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mflr r12
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.cfi_register lr,r12
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get_datapage r10
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mtlr r12
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.cfi_restore lr
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#endif
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#ifdef CONFIG_PPC64
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lwz r7,CFG_DCACHE_BLOCKSZ(r10)
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addi r5,r7,-1
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#else
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li r5, L1_CACHE_BYTES - 1
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#endif
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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#ifdef CONFIG_PPC64
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lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
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PPC_SRL. r8,r8,r9 /* compute line count */
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#else
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srwi. r8, r8, L1_CACHE_SHIFT
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mr r7, r6
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#endif
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crclr cr0*4+so
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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#ifdef CONFIG_PPC64
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add r6,r6,r7
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#else
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addi r6, r6, L1_CACHE_BYTES
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#endif
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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#ifdef CONFIG_PPC64
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lwz r7,CFG_ICACHE_BLOCKSZ(r10)
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
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PPC_SRL. r8,r8,r9 /* compute line count */
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crclr cr0*4+so
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beqlr /* nothing to do? */
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#endif
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mtctr r8
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#ifdef CONFIG_PPC64
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2: icbi 0,r6
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add r6,r6,r7
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#else
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2: icbi 0, r7
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addi r7, r7, L1_CACHE_BYTES
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#endif
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bdnz 2b
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isync
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li r3,0
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blr
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3:
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crclr cr0*4+so
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sync
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icbi 0,r1
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isync
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li r3,0
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blr
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.cfi_endproc
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V_FUNCTION_END(__kernel_sync_dicache)
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